怎样去实现ROS机器人的定位导航呢？如何对ROS机器人的定位导航进行仿真？
2021-12-23 09:22
://e2e.ti.com/blogs_/b/analogwire/archive/2013/03/08/dac-essentials-the-pursuit-of-perfection.aspx欢迎阅读全系列 DAC基础知识文章！
2018-09-18 13:22
什么是纯追踪算法？
2021-11-22 06:08
最近碰到了让我困惑一段时间的事情。从某种意义上说，我有一个非常规则的设计，基本上它是一个小的 块沿着一条线复制粘贴。如同，长（192位）进位链带解码阶段。解码块是12位的块，所以那里 是沿着整个进位链处理的16个解码块中的16个全部192位。我有RLOC，LOC和BEL的所有元素，所以它是关于我可以得到它。现在大多数设计都符合时间要求限制。然而路径2确实失败了。失败的路径是其中的一部分解码块。由于进位链跨越多个时钟区域，起初我认为它可能与这些时钟区域有关。但经过一番 在fpga编辑器中更多的挖掘我注意到它的失败路径 与其他路由相比，路由有点不同。请参阅随附的fpga编辑器截图...所以这些是两片，都在同一个CLB中。弹跳的红线跨越是失败的道路。正如你可以看到从下面的4条路线切片都有一个3的扇出，一个用于上部切片中的每个LUT它路由到。所以你在截图中看到的是12条彩色路径总数，其中只有1个失败。我仍然没有发现为什么这条路线决定反弹 （并且不符合时间），而对于所有其他人在相同的块中没有问题。知道这可能是什么？我此刻的猜测是路由饥饿（不再是特定类型的路由），但是那么为什么在这两个解码块中只有2条路由失败而且为所有 其他14个街区没有问题？与此相关，是否有办法获得有关路由资源的报告用于ISE？如果我能得到每个切片的报告，总结了如何使用了每种类型的大部分路由资源，我可以找到它更快的事情，没有花费一个小时+在fpga编辑器追踪下行路径。以上来自于谷歌翻译以下为原文recently ran into something that had me puzzled for a while. I had a very regular design in the sense that essentially it was a small block copy-pasted along a line. As in, a long (192 bit) carry chain with a decode stage. The decode block was in chunks of 12 bits, so there were 16 of those decode blocks along the entire carry chain to handle all 192 bits. I had all elements in place with RLOCs, LOCs and BELs, so it was about as regular as I could get it. Now most of that design met the timing constraints. However paths 2 did fail. The failing paths were parts of the decode blocks. Since the carry chain spans multiple clocking regions, at first I thought it it might be related to these clocking regions. But after some more digging in fpga editor I noticed that for the failing paths it did the routing a bit different compared to the rest. See the attached fpga editor screenshot... So these are 2 slices, both in the same CLB. The red line that bounces across is the failing path. As you can see the 4 routes from the lower slice all have a fanout of 3, one for each LUT in the upper slice that it routes to. So what you see in the screenshot is 12 colored paths total, of which only 1 is failing. I still haven't found out why for this route it decides to bounce across (and not meet timings) while for all the others in identical blocks there is no problemo. Any idea what this can be? My guess at the moment was routing starvation (as in no more routes of a particular type), but then why do only 2 routes fail in 2 of these decode blocks while for all the other 14 blocks there is no problem? And related to that, is there a way to get a report on routing resource usage in ISE? If I could get a report for each slice that summed up how much of the routing resources of each type was used I could find this sort of thing quicker, without spending an hour+ in fpga editor tracing down paths.
2018-10-09 15:31
