我遇到一个奇怪的问题，当我点击工具图标时，它会立即在翻译，地图和布局布线图标上显示一个复选标记，但实际上并没有做任何事情。当我启用xplorer时，这首先发生，现在即使它被禁用，这个问题仍然存在。它
2018-10-08 17:36
平台：iMXRT595开发工具包：SDK_2_11_1_EVK-MIMXRT595Xtensa Xplorer IDE 版本：8.0.15 WindowsDSP 应用：Hello world我正在
2023-04-10 08:33
我使用的是 NXP MIMXRT685 EVK 板。 我正在尝试创建一个简单的程序来在 DSP 和 ARM 部件之间进行通信。我在 MCUXpresso 和 Xplorer IDE 上使用基本示例
2023-05-18 08:04
我无法找到固件用于以太网PICTAIL DAUGHTER BOARD(AC164123)与浏览器16位开发板的接口，经历了最新4版本的MLA，但是对于TCP/IP只有WiFi支持。我正在使用PIC24FJ256GB110 pim与xplorer16位开发板。预先感谢。
2020-03-17 10:34
我正在 MIMXRT685-AUD-EVK 板上开发一个项目。在 MCUXpresso 的“MIMXRT600 的 Xplorer 入门”之后，我让
2023-03-23 07:08
我关注了 startnow 视频系列，并且能够使用 MCUExpresso IDE 和 Xtensa Xplorer IDE 调试 dsp_mu_polling_hifi4 示例。但是现在，当我重新
2023-03-20 06:36
嗨，我正在使用Virtex II Pro和ISE 8.2.03i。我的设计不符合时序限制，我尝试在ISE中多次使用PAR选项，但没办法。拜托，你能告诉我怎样才能满足时间限制吗？感谢帮助。最好的祝福。以上来自于谷歌翻译以下为原文Hi, I'm using Virtex II Pro and ISE 8.2.03i. My design don't meet timing constraints and I tried multiples PAR options in ISE but no way. Please, Can you tell me what can I do to meet timing constraints ? Thanks for help. Best Regards.
2018-09-28 16:56
我在时序改进向导中读到，手动复制源可以减少扇出。任何人都可以解释复制源的含义吗？还有一个选项来设置最大扇出，我在合成属性对话框中默认为100000，而我在某处读到默认最大扇出为100.我不明白100000是否意味着100？如果我想要一个扇出为25的寄存器自动重新复制，那么我应该将最大扇出数减少到24或以下吗？非常感谢你！问候。消息由koyel.xilinx于03-31-2009 03:32 PM编辑以上来自于谷歌翻译以下为原文I read in the timing improvement wizard that manually replicating a source reduces fanout. Can anyone explain what is meant by replicating the source? Also there is an option to set the maximum fanout, which I see is 100000 by default in the synthesis properties dialog box whereas I read somewhere that maximum fanout is by default 100. I do not understand if 100000 means 100? If I want a register having a fanout of 25 to be replcated automatically then should I reduce the maximum fanout number to 24 or something below? Thank you very much!Regards.Message Edited by koyel.xilinx on03-31-2009 03:32 PM
2018-10-10 11:50
大家好，我正在使用Xilinx ISE 14.7（针对Virtex5，因此没有Vivado），并且遇到了工具的问题，因此更改设计中的信号名称会影响实现，从而影响时序，在某些情况下会略有变化比如说，一个计数器可以在一个设计舒适的时间和一个非常糟糕的失败之间产生差异。有没有人经历过这个？我以前曾经多次遇到这个问题，但总是设法说服自己有另一个潜在的原因，因为我不想相信这些工具会如此挑剔。我现在有一些非常具体的例子，并且发现信号名称本身并不重要，而是名称中的字符数量！例如，两个设计不同的是一个叫做“j”和“jjj”的信号可能有很大不同的时序结果，而“jjj”和“ctr”不同的设计将是相同的。此外，从比较报告看，差异源于映射工具，因为综合似乎推断出不同设计的相同输出。我仍然希望能给出一个更合乎逻辑的答案，否则如果您需要随机更改信号名称以满足时序，这会给时序收敛带来新的挑战！我很想听到任何意见或解决方案......干杯，格伦。以上来自于谷歌翻译以下为原文Hi all, I am using Xilinx ISE 14.7 (targetting Virtex5, hence no Vivado), and have come across a problem with the tools whereby changing names of signals within the design has an impact on the implementation, and hence timing, and in some cases a slight change in the name of, say, a counter can make a difference between a design comfortably timing and failing quite badly. Has anybody else experienced this? I had come across this several times before, but always managed to convince myself that there was another underlying reason, as I did not want to believe that the tools could be so picky. I now have some very concrete examples of this now, and have discovered that it is not the signal name itself that matters but the number of characters in the name! For example, two designs differring by one signal called 'j' and 'jjj' can have vastly different timing results, whereas designs differing by 'jjj' and 'ctr' will be identical. Also, from comparing reports it appears that difference originates from the mapping tool, as synthesis appears to infer an identical output for the different designs. I am still hoping that that a more logical answer can be given, as otherwise this adds a new challenge to timing closure if you need to also randomly change signal names in order to meet timing! I would love to hear any comments or solutions ... Cheers, Glenn.
2018-11-02 11:14
我在ISE 14.7上运行SmartXplorer以优化时序性能。结果显示，7种策略中有4种的时间分数为0.在这些情况下，最坏情况的松弛是：0.112ns MapRunTime0.108ns MapLogicOpt0.108ns MapLogOptRegDup0.270ns MapExtraEffort2SmartXplorer说MapRunTime是最好的策略。 MapExtraEffort2不应该是最好的，因为它具有最高的最坏情况下的松弛？谢谢，约翰以上来自于谷歌翻译以下为原文I am running SmartXplorer on ISE 14.7 to optimize timing performance.The results show that 4 of the 7 strategies have a timing score of 0.In these cases, the worst-case slacks are:0.112ns MapRunTime0.108ns MapLogicOpt0.108ns MapLogOptRegDup 0.270ns MapExtraEffort2 SmartXplorer says that MapRunTime is the best strategy.Shouldn't MapExtraEffort2 be the best since it has the highest worst-case slack? thanks,John
2018-11-09 11:43
