嗨，首先，我使用xdl -ncd2xdl test.ncd生成xdl文件进行读取。然后，在xdl文件上没有任何更改，我使用xdl
2020-04-22 06:57
的一些信息如下：***使用args -secure -ncd2xdl -nopips“system_stub_routed.ncd”“system_stub_routed.xdl”运行xdl版本
2018-11-27 14:37
/xdctools_3_31_02_38_core/packages;..; gmake.exe: *** [package/cfg/am335x_app_pa8fg.xdl] Error 1
2018-05-15 02:37
: Library not found: ti.drv.srio.anull gmake.exe: *** [package/cfg/mySRIOProject_pe674.xdl] Error 1
2018-06-21 04:06
hello_p66.cfg line 754 hello_p66.cfg line809hello_p66.cfg line741gmake.exe:hello_p66.xdl error 1js:xdctools
2018-06-24 07:18
我正在使用netgen来创建后PAR模拟模型。我想知道是否有办法让netgen（或其他工具）输出哪些信号通过哪些开关盒的信息。我可以通过FPGA编辑器直观地看到这一点，但想知道是否有基于文本的信息形式。以上来自于谷歌翻译以下为原文I am using netgen to create post-PAR simulation models. I was wondering if there is any way to get netgen (or some other tool) to ouput the information about which signals go through which switch boxes. I can see this visually with FPGA Editor but wondered if there was a text-based form of that information.
2018-10-16 14:16
PAR可以多次运行，每次递增路由（-k选项）。有没有办法在这些运行之间向NCD添加DIRT约束？我的设计需要很长时间才能通过MAP，但路由速度相当快。我想运行MAP，执行部分路由，将这些路由锁定为DIRT约束，然后完成路由。现在好像我必须再次运行MAP才能插入DIRT约束......有什么方法可以解决这个问题吗？以上来自于谷歌翻译以下为原文PAR can be run multiple times, routing incrementally each time (-k option). Is there any way to add DIRT constraints to the NCD between these runs? I have a design that takes a very long time to go through MAP, but routes rather quickly.I'd like to run MAP, do a partial route, lock down those routes as DIRT constraints, and then finish the routing.Right now it seems like I have to run MAP again in order to insert the DIRT constraints... is there any way around this?
2018-10-11 14:46
本帖最后由 一只耳朵怪 于 2018-6-21 15:29 编辑 我板子AM335x ICEv2，下载了最新的sy***ios_ind_sdk，想要编译Building Full Feature EtherCAT Application，按照手册说明进行到到第五步，发现ecat_def.h没有TIESC_APPLICATION定义啊，是不是我哪里弄错了。谁有完整版本编译好的给我发一下啊。我邮箱007afei@163.com，谢谢。5. Define macros in ecat_appl\EcatStack\ecat_def.h as required for your application. (a) Ensure that TIESC_HW isset to 1. (b) For running default application, set TIESC_APPLICATION to 1 and CiA402_DEVICE to 0. ForSYSBIOS Industrial SDK 02.01.01 User Guide 35running CiA402 application, set TIESC_APPLICATION to 0 and CiA402_DEVICE to 1.
2018-06-21 06:02
/all_p674.xdl] 错误 1gmake: *** [/home/administrator/ti-ezsdk_dm814x-evm_5_04_00_11/component-sources
2018-06-07 08:06
嗨，我可以使用UCF文件更改切片参数吗？例如，我想将我的寄存器类型编辑为“FF”或“LATCH”。我还没有在Xilinx的约束指南中找到它。谢谢。阿卜杜拉以上来自于谷歌翻译以下为原文 Hi, May I change slice parameters using UCF file? For example, I want to edit my register type as "FF" or "LATCH". I couldn't find it in constraints guide of Xilinx yet. Thank you. abdullah
2019-01-14 11:20
