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  • 51单片机在下降沿来之前提前触发外部中断

    #include #include #include#define u3 XBYTE[0xfdf3]//通过A0、A1,写控制字#define wru3_y XBYTE[0xfdf0]//通过A0

    2016-07-11 12:05

  • 使用UART和DMA块时出现问题

    你好,我使用CYC8CKIT-048 PSoC模拟协处理器先锋套件,并且在使用同一个项目中同时使用UART和DMA块的同时遇到问题。我需要使用从PC发送的数字数据,并通过UART接收来确定应该产生哪一个频率正弦波(基本上我需要做一个FSK调制器)。我试图通过将UARTHARTX连接到TCPWM的开关输入端,使用一个引脚作为UART的数字输出,一个引脚作为PWM的数字输入并通过导线连接它们。我计划使用PWM作为时钟分频器(因为PSoC没有数字复用器,或者我找不到它)?根据开关输入的值来计算不同的值。然后,我将PWM线路输出连接到DMA触发输入,DMA将数据从正弦LUT表传输到VDAC的内部寄存器,并将VDAC路由到输出引脚。但是,当我尝试构建这个项目时,我会发现一个错误,即Palter无法找到PIN和固定功能块的有效位置。有没有办法像我想象的那样做,还是我错过了什么?谢谢这里是一个Palel.txt文件的副本:第4阶段E2809:无法找到用于PIN和固定功能块的有效位置。有关详细信息,请参阅报表文件中的数字放置详细放置消息部分。I27 22:不能放置以下实例:pWMY1:CyM0S8O-TCPWMY1(0个位置)时钟块(1个位置):f(时钟,0)\UARTAR1:SCB(3个位置(S):F(SCB,0)F(SCB,1)F(SCB,2))固定功能块和引脚放置:P1〔1〕:Pin 2(0)F(HalfAb,0):\VDACH1:UAB:HalFuAbF(P4PREFCELL,0):CyDeWieldVeloGeRealEngressP4〔1〕:PiNi3(0)F(CKLYGEN,0):CcLogGAND块F(OA,2):\VDACH1:OutHuffel:CyspSO44Abuf\\P0〔4〕:Pin 1(0)P1〔2〕:Pin 4(0)E2055:设计过程中发生错误。 以上来自于百度翻译 以下为原文Hi,I am using CYC8CKIT-048 PSOC Analog Coprocessor Pioneer Kit and am experiencing issues while using both UART and DMA block in the same project.I need to use the digital data sent from a PC and received via UART to determine which frequency sine wave should be generated (basically I need to make a FSK modulator).I was trying to do that by connecting UART_tx to the switch input of a TCPWM by using one pin configured as digital output for UART and one as digital input for PWM and connecting them (by wire). I was planning to use the PWM as a clock divider (since this PSOC doesn't have a digital mux, or I can't seem to find it?) which counts to different values depending on the value of switch input.Then i would connect PWM line output to DMA trigger input, and DMA would transfer data from a sine LUT table to VDAC's internal register and route VDAC to an output pin.But when i try to build the project I get an error saying that the placer is unable to find a valid placement for pins and fixed-function blocks. Is there a way to do this the way I imagined, or am I missing something? Thanks Here is a copy of placer.txt file:Phase 4E2809: Unable to find a valid placement for pins and fixed-function blocks. See the Digital Placement's Detailed placement messages section in the report file for details.I2722: The following instances could not be placed:\PWM_1:cy_m0s8_tcpwm_1\ (0 location(s))ClockBlock (1 location(s): F(Clock,0))\UART_1:SCB\ (3 location(s): F(SCB,0) F(SCB,1) F(SCB,2))Fixed function block and pin placement:P1[1]: Pin_2(0)F(HALFUAB,0): \VDAC_1:UAB:halfuab\F(p4prefcell,0): CyDesignWideVoltageReferenceP4[1]: Pin_3(0)F(CLK_GEN,0): ClockGenBlockF(OA,2): \VDAC_1:OUTBUFFER:cy_psoc4_abuf\P0[4]: Pin_1(0)P1[2]: Pin_4(0) E2055: An error occurred during placement of the design.

    2018-11-22 17:09