编程选项字节或修改我的固件？谢谢 #sequence #stm8 #timer＃option-bytes #led #wiping #toggle #turn＃stm8af6266以上来自于谷歌翻译以下
2019-01-15 13:06
我刚刚安装了一个新的系统并安装了MPLAB XIDE 4.01，我的真正的ICE并没有显示在一个项目上作为调试选项。PkIIT 3是显示调试选项的唯一项目。真正的ICE显示在MPLAB IPE中作为一个选项。这个系统从来没有任何其他版本的MPLAB。我尝试过UNIN。暂停司机和更新驱动程序。我已经卸载/重新安装程序没有成功。有没有其他人遇到这个问题，它是如何固定？ 以上来自于百度翻译 以下为原文 I just setup a new system and installed MPLAB XIDE 4.01 and my Real ICE does not show up as a debug option on a project.PICKIT 3 is the only item showing as a debug option.The Real ICE shows up in MPLAB IPE as an option.This system has never had any other version of MPLAB on it. I have tried to uninstall the driver and update the driver.I have uninstalled / reinstalled the program several times without success.Has anybody else run into this and how did it get fixed?
2019-01-02 16:45
to all the modes. 1) If I toggle RST_N, the RAM would be initialized to zeros, wiping the previously
2018-11-22 17:11
在设置代码时，PIN设置似乎不会被可靠地过滤掉。我使用的是和声2.04和插件2.05.2有什么建议吗？它花费了我足够的时间从非工作的PIN设置追踪bug。 以上来自于百度翻译 以下为原文 Pin settings don't seem to be filtering down reliably when generating code. I am using harmony 2.04 and plugin 2.05.2. Any suggestions?It has cost me enough time now chasing bugs from non working Pin Settings.
2018-09-21 10:23
你好，我有一个PIC 16F18325，它必须在非常特定的时间和相当高的频率下从两个不同的ADC通道采样，我想用同一个TMR上的两个CCP模块和一个从CPCSI的脉冲产生ADC的自动触发的CLC模块来解决它。D我应该有足够的时间来做所有的事情，但是我在数据表上也找不到其他的问题，如果我（自动触发器）第一次设置ADC的GONNDONT位，在它完成之前（当位已经被设置）我（再次，自动触发器）再次设置时，会发生什么？转换会从开始重新开始，因此需要更长的时间来完成吗？将忽略它并继续转换已经进行，因此需要通常的时间完成吗？其他？也许是错误？我想第二个，但在数据表中没有一个明确的答案，所以我问你的经验，我知道这是一个非常极端的情况，在我的真实情况下它永远不会发生，我只是好奇，如果我必须考虑到它的任何特殊方式，使代码更重。谢谢！ 以上来自于百度翻译 以下为原文 Hello, I've a PIC 16F18325 that it has to sample from two different ADC channel at very specific times and quite high frequency, I've thought to solve it using two CCP modules on the same TMR and a CLC module that generates the auto-trigger for the ADC from the pulse of the CCPs I've done the math and I should have enough time for everything, but I have some question I cannot find on the datasheet nor in other forums what happens if, I (the auto-trigger) first set the GO_nDONE bit of the ADC, and before it has completed (so while the bit is already set) I (again, the auto-trigger) set it again? will the conversion restarts from the beginning and therefore it require a longer time to complete?will simply ignore it and continue the conversion already in progress and therefore takes the usual time to complete?other? maybe errors? I suppose the second but there isn't a clear answer to this situation in the datasheet so i'm asking to your experience I know it is a quite extreme situation, and in my real case it should never happens, i'm just curious if I have to take in account of it in any special way to make the code more reliable Thank you!
2019-06-03 11:13
我们购买了二手MSO7000A，其中包含许多已安装的选件许可证，其中包括SEC选项，可防止将示波器设置持久保存到内部存储器。当我连接它时，USB存储器似乎也没有显示为文件系统的一部分，所以基本上甚至没有一种不方便的方法来保存这台机器上的设置。我们根本不需要SEC选项 - 有没有办法卸载它或以其他方式将其关闭？ 以上来自于谷歌翻译 以下为原文We purchased a used MSO7000A with many installed option licenses, including the SEC option which prevents persisting the scope settings to internal memory. It also appear that USB storage is not showing up as part of the filesystem either when I attach it, so basically there is not even an inconvenient way of saving the settings on this machine. We have no need for the SEC option at all here - is there a way to uninstall it or otherwise turn it off?
2018-11-26 09:16
首先，我使用的是XC16V1.31和MPLAB X V3.65的PIC24FV32 KA302。我有一个奇怪的优化行为，其中只有15个成员的结构只在优化级别设置为1时才使前5个成员消失。这个结构是字符串（char *），后面是一些无符号整数。这是一个刚刚开始出现的新行为，我不确定我能做些什么。我曾试图声明结构不稳定，但似乎没有效果。该变量在结构中的数据甚至未被访问的点上被篡改。我输入一个不相关的函数，中间的结构成员被抹去0。每一次运行时，它的精确点似乎不同，尽管这可能是因为我用优化的代码用ICD3进行调试。除了构建没有优化，还有什么可以尝试的吗？我希望至少有一些大小的优化，因为CODISACACE与应用程序的大小相当小。 以上来自于百度翻译 以下为原文 Hi all, First things first, I'm using a PIC24FV32KA302 with XC16 v1.31 and MPLAB X v3.65. I'm having a weird optimization behavior where a structure with 15 members is getting the first 5 members wiped out only when Optimization Level is set to 1.The structure is as string (char*) followed by a number of unsigned integers. This is a new behavior that just started to crop up, and I'm not sure what I can really do about it.I've attempted to declare the structure volatile but it seems to have no effect.The variable is getting clobbered at a point where the data in the structure isn't even being accessed.I enter an unrelated function, and midway through it the structure members in question get wiped out to 0.The exact point seems to differ each time I run through it, although this could be since I'm debugging with an ICD3 with optimized code. Is there anything else I can try other than just building without optimization?I'd prefer to have at least some size optimization, as codespace is rather slim with the size of this application. Any advice would be appreciated, Thanks!
2019-01-30 11:03
背景：MPLAB X IDE 3.65、XC32 V1.43、和声V2.03B、定制板使用PIC32 MZ2064 DAH176、NEWHAVEN NHD-4.3-48022EF-ASXNα-T显示（4.3）、480X227像素、4线触摸触摸屏等，我理解切换屏幕是一种计算昂贵的方法，但我对什么是好奇完成事情的最佳实践？这就是我要做的。首先，创建启动飞溅屏幕。这是非常好的，因为我使用的是内置的硬件加速。这个屏幕将持续大约4-5秒，然后转换到主屏幕。我注意到每个屏幕都会有3个新的层，因为开关屏幕会把所有东西都拆掉，重新开始。问题是，当它必须转变时，你可以看到LCD涂料。咖啡制造商的演示也是如此。让我的主屏幕仅仅是另一个层，然后在幕后移除旧的引导飞溅层会更好吗？此外，从主屏幕，我将有按钮，将用户到不同的配置屏幕，并回到完成。这应该是一个新的屏幕还是另一个层？ 以上来自于百度翻译 以下为原文 Background: MPLAB X IDE 3.65, XC32 v1.43, Harmony v2.03b, custom board using PIC32MZ2064DAH176, Newhaven NHD-4.3-480272EF-ASXN#-T display (4.3", 480x272 pixel, 4 wire resitive touchscreen) I understand that switching screens is a computationally expensive method, but I am curious as to what are the best practices for getting things done? Here is what I'm looking to do. First, create a boot splash screen. This has worked extremely well now that I use the hardware acceleration that is built in. This screen would last about 4-5 seconds and then transition to a main screen. I noticed that each screen gets 3 new layers as switching screens will tear everything down and start anew. The problem is that you can see the LCD paint when it has to transition. This is true of the coffee maker demo as well. Would it be better to make my main screen just another layer and then remove the old boot splash layer behind the scenes? Also, from the main screen, I will have buttons that will take the user to different configuration screens and back upon completion. Should this be a new screen or another layer?
2019-02-14 15:13
嗨， 我尝试在Vivado 2013.4中构建我们的设计并构建Xilinx JESD204B设计示例，我收到以下错误：错误：[Common 17-69]命令失败：此设计包含不支持比特流生成的内核：i_jesd204_tx_support_block / jesd204_i / inst / i_jesd204_tx（jesd204_txjesd204_v5_1_top）执行时“write_bitstream -force jesd204_tx_example_design.bit”我的许可证经理似乎表明我们的JESD204B核心许可证仍然有效（至少到2013年12月）。许可证管理器显示IP：Design_Linking许可证为jesd204，版本限制为2013.12，到期日期为永久，许可证类型为Nodelocked，Count为Uncounted，Information为License_Type：Design_Linking; ipman，jesd204，ip，permanent，_0_0_0，文件名为/opt/Xilinx/Vivado/2013.4/data/ip/core_licenses/Xilinx.lic，主机ID为ANY，主机ID匹配为是，许可CRC为好，搜索顺序为7。注意：我之前在许可证管理器中有一个条目似乎与版本限制为2013.06的ISE有关，该版本限制在目录/opt/Xilinx/Vivado/2013.4/ids_lite/ISE/coregen/core_licenses/xilinx.lic中。我删除了这个文件，我不再在许可证管理器中看到JESD204条目了。许可证服务器上是否有与我看到的许可证版本日期冲突的信息？我得到的印象是，此错误仅适用于我们没有的模拟许可证。任何人都可以确认核心是否过期，如何检查？谢谢，特雷弗以上来自于谷歌翻译以下为原文Hi,I have tried building our design and building the Xilinx JESD204B design example in Vivado 2013.4 and I get the following error: ERROR: [Common 17-69] Command failed: This design contains a core for which bitstream generation is not supported:i_jesd204_tx_support_block/jesd204_i/inst/i_jesd204_tx (jesd204_txjesd204_v5_1_top) while executing"write_bitstream -force jesd204_tx_example_design.bit" My license manager seems to indicate that our license for the JESD204B core is still valid (at least until December 2013).The license manager shows an IP:Design_Linking license for jesd204, version limit is 2013.12, expiration date is Permanent, License type is Nodelocked, Count is Uncounted, Information is License_Type:Design_Linking;ipman,jesd204,ip,permanent,_0_0_0, File Name is /opt/Xilinx/Vivado/2013.4/data/ip/core_licenses/Xilinx.lic, Host ID is ANY, Host Id Matches is Yes, License CRC is Okay, Search Order is 7. Note:I previously had an entry in the license manager that seemed to relate to ISE that had a version limit of 2013.06 that was in the directory /opt/Xilinx/Vivado/2013.4/ids_lite/ISE/coregen/core_licenses/xilinx.lic.I removed this file and I do not see that JESD204 entry in the license manager any more.Could there be information on the license server that conflicts with the license version dates that I see? I got the impression that this error applies to simulation licenses only which we don't have.Can anybody confirm whether the core is expired, how to check for sure? Thanks,Trevor
2018-12-10 10:39
