is negative, in such case I substract 2^16 to convert from 2's complement number to decimal. Finally I
2019-05-16 15:44
substract the Reference Measurement from the last measurements. so I got 10dB 20dB and 50dB: 2 Way
2018-11-02 09:44
单片机常用汇编语言助记符英文全称
2021-03-29 06:29
你好，我用的是一个带有DSSP33的USB堆栈。我从计算机发送一定数量的字节，但是这个函数总是返回64（完整的缓冲区），甚至实际上发送较低的字节数。有没有办法确切知道我确实收到多少字节？UsButhHunle＝HIDXXPATH（CuthOpDeice），ReceivedDataBuffer（Unt8E*T*），CuffyApEpsith/** 64 */；RxyLeN＝UbHuffReLeTeTeLead（USBOutHandle）； 以上来自于百度翻译 以下为原文 Hi, I am using USB stack with a dspic33. I am sending a certain number of bytes from the computer, but this function always returns 64 (the complete buffer) even sending actually a lower amount of bytes. Is there any way to know exactly how many bytes I do really receive? USBOutHandle = HIDRxPacket(CUSTOM_DEVICE_HID_EP, (uint8_t*)&ReceivedDataBuffer, CUSTOM_EP_SIZE/*64*/); rx_len = USBHandleGetLength(USBOutHandle);
2019-05-14 15:19
codegen介绍
2021-02-02 06:20
你好，我试图用交流信号馈入PSoC和我有疑问怎么办。我配置了PSOC：3-OPAM和ADCVRR。交流信号提供由文氏振荡存在GND有。我不知道如果我有文氏振荡器的设计考虑到AGND的PSoC（2.5V）。现在我试着喂养的原理与AGND的调查（refmux）和noinv +直接与文氏振荡器的输出。这个方法正确吗？谢谢你的支持！当做。 以上来自于百度翻译 以下为原文Hi, I'm trying to feed the PSoC with an AC signal and I have doubts how to do it. I configured the PSoC with: 3-OPAM and ADCINVR. The AC signal is providing by a wien oscillator so exist a gnd there. I don't know if to design the wien oscillator I have to take in account the AGND (2.5V) of the PSoC. Now I'm trying feeding the INV- of INSAMP with AGND (refmux) and NOINV+ directly with the output of the wien oscillator. Is this method right? Thanks for your support! Regards.
2019-03-22 07:47
例如，如果我在下面的图片中有类似的东西。每个实体将另一个实体输出作为输入数据，但是在时钟的上升沿运行。我的问题是，流程将在一个clokc循环中完成吗？当我得到我的B结果。在第一个时钟周期发生什么，然后在第二个时钟周期发生什么。或者我应该从此过程中删除时钟，以使其对先前实体的输出做出反应。以上来自于谷歌翻译以下为原文For example, if I have something like on the picture below. Each entity takes another entity ouput as input data, but is operating on clock's rising edge. My question is, will process be finished in one clokc cycle? When I got my B result. What happens at first clock cycle, then at second, at third. Or should I remove clock from this process, to make it reacting on previous entity's output.
2019-03-26 09:23
对于我们的项目，我们使用CurPress芯片43362的村田SN80UFL模块。我们的仪器运往世界各地，因此我们必须在许多国家进行一些法规测试。为此，我们使用加载到芯片的43362A2-MFGTest.Bin文件和WL工具，我们可以与芯片进行通信。原则上，与模块的通信工作是因为我们获得了“CurueEthAdDR”命令的正确值，并且传输模式也在正常工作。但是接收模式似乎不起作用。我们使用下面的脚本来激活模式：\\WLLoo\\WL43362A2.EX-串行27向下\\WLLoo\\WL43362A2.EX-串行27 MPC 0\\WLLoo\\WL43362A2.EX-串行27国家所有\\WLLoo\\WL43362A2.EX-串行27扫描抑制1\\WLLoo\\WL43362A2.EX-串行27通道1\\WLLoo\\WL43362A2.EX-串行27 BI 65535\\WLLoo\\WL43362A2.EX-串行27向上但我们总能看到有一个永久的可见峰。附上你可以找到测量。峰值的频率也根据配置的信道号而改变。因此，韩国测试失败，因为我们总是超过-57 dBm的限制。通常在接收模式下不应该有可见的峰值。我们已经与村田接触了几个星期，但不幸的是没有成功。他们建议在塞浦路斯论坛上发布这个问题，因为这与芯片本身有关。你能支持我们吗？你知道什么是错的吗？接收量20180619.PNG19.3 K 以上来自于百度翻译 以下为原文For our projects we use the Murata SN8000UFL module with the Cypress chip 43362. Our instruments are shipped world-wide therefore we have to perform in many countries some regulation tests. For this we use the 43362a2-mfgtest.bin file that is loaded to the chip and by the WL tool we can communicate with the chip. In principal the communication with the module works due we get for commands like "cur_etheraddr" the correct values and also the transmit mode is working correctly. But the receive mode seems not to work. We use following script to enbale the mode:..\\wl_tool\\wl43362A2.exe --serial 27 down..\\wl_tool\\wl43362A2.exe --serial 27 mpc 0..\\wl_tool\\wl43362A2.exe --serial 27 country ALL..\\wl_tool\\wl43362A2.exe --serial 27 scansuppress 1..\\wl_tool\\wl43362A2.exe --serial 27 channel 1..\\wl_tool\\wl43362A2.exe --serial 27 bi 65535..\\wl_tool\\wl43362A2.exe --serial 27 up But we always can see that there is a permanent peak visible. Attached you can find the measurement. The frequency of the peak is changing also depending on the channel number that is configured.Therefore the Korea tests fail due the we always exceed the limits of -57dBm. Normally in the receive mode there should be no peak visible. We are already in contact with Murata since several weeks but unfortunately with no success. They have proposed to post this issue in the cypress forum because this is related to the chip itself.Could you please support us? Do you have any idea what is wrong? Receive_Peak20180619.PNG 19.3 K
2018-09-07 11:31
