。 以上来自于百度翻译 以下为原文 I'm trying to get a PIC32MX to enumerate, but all it sees are bit stuffing
2019-06-19 07:08
workstation to solder/stuff FPGAs but i cannot find any reflow profile for FPGA stuffing. Can anyone give me
2019-05-28 11:06
基于 的XC3S1OOE FPGA的USB接口IP核模块设计和验证
2020-12-25 06:48
嗨，我有一台HP 8752A（选择003和010），有什么方法可以看到这个单元的S参数吗？ 以上来自于谷歌翻译 以下为原文Hi, I have an HP 8752A (opt 003 and 010), is there any way I can see S-parameters with this unit?
2019-02-21 14:58
NUC240/NUC140/NUC130在电梯控制器和监测的应用设计
2020-12-18 07:36
CAN Bus(Controller Area Network)，控制器区域网，起源于80年代，由国际标准化组织(ISO)所发布，因为利用双线差动(two-wired differential)，使其即使在电器条件恶劣环境下，也可正常运作的一种传输总线。又因双线沟通的特性，大幅缩减了其应用线路的使用量，也降低传统线路复杂易造成错误的发生机会。基于以上特性，CAN Bus一大应用层面即被导入于汽车工业，因传统的汽车使用线路复杂，使得早期汽车内部线路易于发生故障时且较难以排除。因此双线差动讯号式CAN Bus的电器特性即被快速导入并广泛运用在各交通工具领域(航空、轮船与汽车)或是工业控制。
2019-07-09 08:06
您好。我想用PIC（特定PIC16F179）将十六进制生成的代码上传到另一个PIC。我想到的一个解决方案是用英特尔HEX格式：BBAAAATDDCC来编译代码。然后，考虑目标PIC的编程规范表，编写一个生成特定符号的程序。对于每一行十六进制产生的代码，ALS，但这看起来是一项非常艰巨的任务。还有别的办法吗？谢谢！ 以上来自于百度翻译 以下为原文 Hello.I want to use a pic(specifically PIC16F1769) to upload hex generated code into another PIC.One solution I thought of is to fragment the code by intel hex format :BBaaAATTDDCC and then, considering the programming specification sheet of the targeted PIC, write a program to generate specific signals for each of the lines of the hex generated code.But this seems like a very labourious task. Is there any other way of doing it? Thanks!
2019-04-04 14:30
我需要一个PIC与快速奴隶SPI能力（最好超过5MHz），I2C主机，至少14个ADC通道（最好是12位），小封装尺寸（＆Gt；＝40PIN）。我也希望PGD/PGC引脚被用作调试UART（当不使用PGD/PGC）时，我不认为PIC16会做什么。单优先级中断方案让我怀疑软件是否能保证SPI服务足够快。我低估了新的PIC16吗？似乎PIC18LF45 K42是理想的，在SPI上具有7.5MHz额定值、2B ADC、全PPS和带有矢量的优先中断的2字节FIFO。5x5mm UQFN-40是有吸引力的。唉，这只是一本至今为止的小册子。我想知道它能用多长时间。所以我看的是PIC18LF45 K40和PIC24F32 KA304。PIC24可以运行10MHz SPI和12B ADC，并且绝对可以完成这项工作。K40可以做6MHz SPI，只有10位ADC，但完全PPS最终可以被K42代替。PIC24是纸上更好的选择，但是6x6mm UQFN-48比K40的UQFN-40大50%，IO计数没有优势。这是一个非常有空间限制的设计。我希望有小的BGA选项。我已经做了很多PIC12，16，18的设计，但还没有用16或32位图片。看看K40的勘误表，我想知道它是否太坏，不打扰，我应该咬更大的包装子弹。马克。 以上来自于百度翻译 以下为原文 I need a PIC with fast slave SPI capability (preferably over 5MHz), I2C master, at least 14 ADC channels (preferably 12bit), and small package size (>=40pin). I'd also like the PGD/PGC pins to be used as a debug UART (when not using PGD/PGC).I don't think any PIC16 will do. The single priority interrupt scheme makes me wonder if software could guarantee to service SPI fast enough. Am I underestimated the newer PIC16's?It seems the PIC18LF45K42 is ideal, with 2byte FIFOs on SPI with 7.5MHz rating, 12b ADC, full PPS, and prioritized interrupts with vectors. 5x5mm UQFN-40 is attractive. Alas it's just a brochure so far. I wonder how long till it's available.So I'm looking at the PIC18LF45K40 and the PIC24F32KA304. The PIC24 can run 10MHz SPI, and 12b ADC, and definitely could do the job. The K40 could do 6MHz SPI I think, only 10bit ADC, but with full PPS could be replaced by the K42 eventually. The PIC24 is a better choice on paper, but the 6x6mm UQFN-48 is 50% bigger than the K40's UQFN-40 with no advantage in IO count. It's a really space constrained design. I wish there were small BGA options. I've done many PIC12,16,18 designs, but not worked with 16 or 32bit PICs yet.Looking at the K40's errata list, I'm wondering if it's too broken to bother with, and I should just bite the bigger package bullet. Mark
2019-03-05 09:47
原谅我的无知，但我是一个来自软件背景的FPGA的n00b。就像这张表上5000张其他n00b海报一样，我想使用我的spartan-3e的以太网功能。没有人在网上实际上有一个现成的复制/粘贴解决方案，这对我来说没问题。我会做的工作并弄清楚。我已经完成了很多功课，但总的来说我对一件事感到困惑......我知道有两种基本的方法可以使用以太网控制器：使用xilinx IDE提供的免费IP核，或者自己编写VHDL / verilog并正确地敲出MII接口。后一种方法显然是一种皇家的痛苦，因为你必须计算校验和，否则操纵TCP / UDP数据包的可能性最低......我的问题是：我的应用程序要求以尽可能低的开销来处理数据包。如果我不需要，我甚至不想等待一个额外的时钟周期。我的理解是，你放在FPGA上的任何*核心*实际上都是一个“软核”处理器，换句话说，存在来自这些不同IP核的强大功能，因为FPGA是用VHDL指令编程的，模拟比如说一个8086 CPU基本上运行用C或程序集编写的虚拟8086程序，因为使用这些语言要比VHDL容易得多。那是对的吗 ？如果是这样，这是否意味着我希望我的整体网络性能比我自己直接写入处理的速度慢？如果没有，那么“核心”可以与直接VHDL程序共存，就像我链接到C中的外部符号一样吗？或核心消耗整个芯片？感谢您抽出宝贵时间回复n00b。我很感激。-n00b以上来自于谷歌翻译以下为原文forgive my ignorance but I'm a n00b to FPGA coming from a software background. Just like 5000 other n00b posters on this form, I want to use the ethernet capabilities of my spartan-3e. Nobody online actually has a ready-made copy/paste solution for this, and that's ok by me. I'll do the work and figure it out. I've already done a lot of the homework, but I'm confused about one thing in general... I'm aware that there are two fundamental ways to use the ethernet controller: using the free IP core that xilinx's IDE offers, or writing VHDL/verilog myself and correctly banging out an MII interface. The latter method is a royal pain apparently because you have to calculate checksums and otherwise manipulate TCP/UDP packets at about the lowest level possible... My question is this: My application requirespackets to be processed with the lowest amount of overhead possible. I don't even want to have to wait one extra clock cycle if I don't have to. My understand was that any *core* that you put on an FPGA is effectively a "soft-core" processor, in other words, the robust functionality from these various IP cores exists because the FPGA is programmed with VHDL instructions that simulate, say, an 8086 CPUthat basically run a program written in C or assembly for this virtual 8086, since it's a lot easier to use these languages than VHDL. Is that correct ? If so, does that mean I would expect my overall network performance to be slower than if I wrote the processing myself in straight-vhdl ? If not, then can a "core" coexist with a straight VHDL program, the same way as I would link to an external symbol in C ? Or does the core consume the whole chip ? Thank you for taking the time to respond to a n00b. I appreciate it. -n00b
2019-05-31 03:31
