]of_find_node_by_phandle+0xa0/0xd4[95.089404] rcu: rcu_sched kthread starved for 26012 jiffies! g-1091
2023-01-29 17:05
]of_find_node_by_phandle+0xa0/0xd4[95.089404] rcu: rcu_sched kthread starved for 26012 jiffies! g-1091
2023-01-10 13:54
原谅我的无知，但我是一个来自软件背景的FPGA的n00b。就像这张表上5000张其他n00b海报一样，我想使用我的spartan-3e的以太网功能。没有人在网上实际上有一个现成的复制/粘贴解决方案，这对我来说没问题。我会做的工作并弄清楚。我已经完成了很多功课，但总的来说我对一件事感到困惑......我知道有两种基本的方法可以使用以太网控制器：使用xilinx IDE提供的免费IP核，或者自己编写VHDL / verilog并正确地敲出MII接口。后一种方法显然是一种皇家的痛苦，因为你必须计算校验和，否则操纵TCP / UDP数据包的可能性最低......我的问题是：我的应用程序要求以尽可能低的开销来处理数据包。如果我不需要，我甚至不想等待一个额外的时钟周期。我的理解是，你放在FPGA上的任何*核心*实际上都是一个“软核”处理器，换句话说，存在来自这些不同IP核的强大功能，因为FPGA是用VHDL指令编程的，模拟比如说一个8086 CPU基本上运行用C或程序集编写的虚拟8086程序，因为使用这些语言要比VHDL容易得多。那是对的吗 ？如果是这样，这是否意味着我希望我的整体网络性能比我自己直接写入处理的速度慢？如果没有，那么“核心”可以与直接VHDL程序共存，就像我链接到C中的外部符号一样吗？或核心消耗整个芯片？感谢您抽出宝贵时间回复n00b。我很感激。-n00b以上来自于谷歌翻译以下为原文forgive my ignorance but I'm a n00b to FPGA coming from a software background. Just like 5000 other n00b posters on this form, I want to use the ethernet capabilities of my spartan-3e. Nobody online actually has a ready-made copy/paste solution for this, and that's ok by me. I'll do the work and figure it out. I've already done a lot of the homework, but I'm confused about one thing in general... I'm aware that there are two fundamental ways to use the ethernet controller: using the free IP core that xilinx's IDE offers, or writing VHDL/verilog myself and correctly banging out an MII interface. The latter method is a royal pain apparently because you have to calculate checksums and otherwise manipulate TCP/UDP packets at about the lowest level possible... My question is this: My application requirespackets to be processed with the lowest amount of overhead possible. I don't even want to have to wait one extra clock cycle if I don't have to. My understand was that any *core* that you put on an FPGA is effectively a "soft-core" processor, in other words, the robust functionality from these various IP cores exists because the FPGA is programmed with VHDL instructions that simulate, say, an 8086 CPUthat basically run a program written in C or assembly for this virtual 8086, since it's a lot easier to use these languages than VHDL. Is that correct ? If so, does that mean I would expect my overall network performance to be slower than if I wrote the processing myself in straight-vhdl ? If not, then can a "core" coexist with a straight VHDL program, the same way as I would link to an external symbol in C ? Or does the core consume the whole chip ? Thank you for taking the time to respond to a n00b. I appreciate it. -n00b
2019-05-31 03:31
