These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.
2010-07-29 16:45
These 8-bit shift registers feature gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete control over incoming data as a low at either input inhibits entry of the new data and resets the first
2010-08-03 20:42
SN54221,SN
2010-08-20 17:26
SN54136,SN54LS136,SN74136,SN74LS136英文资料
2010-08-05 16:36
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing. These devices allow data transmission from the A
2010-07-23 18:09
These devices consist of bus transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
2010-07-22 16:20
These octal bus transceivers are designed for asynchronous two-way communication between open-collector and 3-state buses. The devices transmit data from the A bus (open-collector) to the B bus (3 state) or from the B bus to the A bus,
2010-07-23 18:14
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bid
2010-07-26 17:43
These monolithic BCD-to-decimal decoder/drivers consist of eight inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input date available for decoding by the NAND gates. Full decoding of valid BCD i
2010-08-12 15:45
54S11 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS11 and SN74S11 are chara
2010-08-04 19:36
