嗨，如何消除负面松弛？如果我把时间忽略约束放到松弛路径上，它会破坏逻辑吗？谢谢你以上来自于谷歌翻译以下为原文Hi, How to remove negative slack?. If i put
2019-03-29 12:48
如图所示，clk是源时钟，clk[0]，clk[1]，clk[2]是PLL的输出时钟，其中clk[0]和clk[2]有延迟，这个问题怎么解决？setup time slack和hold time
2015-10-12 17:54
(6.66ns) - ISE says Worst case slack (setup) = -7.858ns, best case achievable = 14.46ns (i.e. 6.66ns
2019-04-04 09:20
internal register,Clock Setupt Slack Time = Data Required Time - Data Arrival TimeData Arrival Time
2013-10-22 22:26
to time I will get slightly negative slack (> -0.1ns). Checking the runme.log with 2017.1, I
2018-11-01 16:13
for implementation. i have a design where the critical path (from souce FD to destination FD) gives a slack
2019-04-08 08:58
be the best since it has the highest worst-case slack? thanks,John
2018-11-09 11:43
----------------------------------- --------------------------------------------- Slack（最慢的路径） ：-0.270ns（需求 - 数据路径）源
2019-07-12 11:31
want to improve the slack for both setup and hold, what is the best strategy I should choose?
2018-11-05 11:40
，抛开什么时钟的抖动以及其他不确定时间，我们可以得到比较理想的reg2reg传输的建立时间和保持时间余量（slack）计算公式：建立时间余量的计算公式：Setup time slack = Data
2015-07-24 12:03
