S32R45EVB： 当我选择“peakSearch_256smp_64crp.pspt”检查第一步（Threshold screening）时，我发现结果并不像预期的那样： 几乎所有偶数
2023-04-23 10:42
目前等同采用IEC 61196-1(1995)的国家标准GB/T 17737.1-2000 标准中，关于屏蔽效率（SCREENING EFFECTIVENESS）有以下几种方法：表面转移阻抗——注入
2019-07-09 08:03
大家好，祝大家新年快乐，我使用PIC24FJ128GA310控制器进行ADC操作。我使用8 MHz作为初级和32 kHz次级振荡器。我使用微芯片代码配置器。我通过串行通信读取ADC输出。我的问题是我阅读的变化。硬件看起来很简单&很好（我附上一张照片）。例如-12位（2^12=4096）ADC对话。对于模拟电压为750毫伏，我得到950位的值。如果我再次读取，它将改变为948或952或955位的值。我试着改变转换时钟或采集时间或TAD。但我还没有达到稳定的价值。如何使用这些值来获得稳定的结果。 以上来自于百度翻译 以下为原文 Hello & a very Happy New Year to all present in the Forum, I am using PIC24FJ128GA310 controller for my ADC operation. I am using 8 MHz as primary & 32 KHz secondary oscillator. I am using Microchip code configurator. I am reading the ADC output through serial communication. My issue is the variations in my reading. Hardware seems to be simple & alright (I am attaching a pics of it). For example- 12 bit (2^12=4096) ADC conversation. For analog voltage of 750 mV, i am getting 950 bit value. If i read once again it is changing to 948 or 952 or 955 bit value. I tried changing the Conversion Clock or Acquisition Time or TAD. But i am yet to reach a stable value. How can i use these values to get a stable result. Kindly guide. RegardsNitE Attached Image(s)[img][/img][img][/img]
2019-05-20 13:08
sure how to determine that from the silk screening on the packaging of the part.I tried both speeds
2019-05-07 13:39
Telematics的应用模式与系统设计要领是什么？
2021-05-17 06:19
数据表规定Vref在“绝对最大额定值”部分下变为0至3.3V，并为不同的逻辑系列指定了许多特定的Vref电平。任何人都知道Vref电平是否有其它限制，这些限制将使用给定的VCCO或VCCAUX电源做一些有用的事情（也就是说，不仅仅是“好，它不会损坏设备......”）？将输入配置为HSTL / SSTL的输入是快速的，片上集成的比较器+ +连接到IO并且 - 连接到Vref？显然，这不符合现有的逻辑系列或规范，但是 - 如果可用的参考范围确实是0到3.3V- 它可以消除在比较器可以的情况下需要大量的片外比较器芯片都使用相同的参考电压。以上来自于谷歌翻译以下为原文The datasheet specifies that Vref goes 0 to 3.3V under the "absolute maximum ratings" section, and it specifies a number of specific Vref levels for different logic families.Anyone know if there are other limits to the Vref levels which will do something useful (that is, more than simply "well, it won't damage the device...") with a given VCCO or VCCAUX supply?Would an input configured as HSTL/SSTL work as a fast, on-chip-integrated comparator with + connected to the IO and - connected to Vref? Obviously that wouldn't be compliant with an existing logic family or specification, but -- if the available reference range really is 0 to 3.3V -- it could eliminate the need for a lot of off-chip comparator silicon in the case where the comparators can all use the same reference voltage.
2019-05-23 09:30
大家好，如果速度不是标准，那么您对高温环境建议哪种速度等级？我们正在评估Spartan-6系列FPGA。通常（从数据表中），最高工作温度的规格低于结温。例如，最大工作温度可以是105℃，相应的温度为125℃。但Xilinx的数据表仅提到工作温度为最大结温。为什么是这样 ？还有关于Spartan-6 FPGA系列温度测试的文档吗？问候萨曼斯以上来自于谷歌翻译以下为原文Hello All, Which speed grade do you suggest for high temperature environment if speed is not a criteria ? We are evaluating Spartan-6 series FPGA. Usually ( as from the datasheet) the specification formaximum operating temperature is lower than junction temperature. For e.g..maximum operating temperature can be 105C for a corresponding junction temperature of 125C. But Xilinx's datasheet only mentions operating temperature as Max Junction temperature. Why is this ? Also any documentation available on Temperature testing of Spartan-6 FPGA families ? RegardsSumanth
2019-07-30 09:02
求大神分享一下软件项目管理的笔记整理
2021-09-23 07:35
