我使用的是MCP795W10-I/SL集成电路。我已经编写了代码并建立了电路（我已经生产了一个PCB）。它很好用。但过了一会儿，它就停下来工作了。我的意思是时间停止了。即使重新启动，它也不会开始工作。当我去掉晶体并解决它时，它又开始工作了。这怎么可能，怎么解决？ 以上来自于百度翻译 以下为原文 I am using MCP795W10-I/SL IC. I have wrote the code and build the circuit (I have produced a PCB). It works fine. But after a while it stops to work. I mean the time stops to advence. Even after restart it is not beganing to work. When I remove and resolder the crystal it began to work again. How this could be possible and how to solve?
2019-03-15 10:35
quirky/non standard as regards line termination characters etc. for GPIB strings for the instrument
2018-09-06 10:09
>如果这个警告只是一个警告我怎么能把它删除？好吧，它可能是任何重大事件都可能导致你的系统崩溃。它取决于组件（仅关闭第一条消息 - 没有看到第二条消息。）我没有看到任何明显的关闭它的方法，除非在运行时可能没有显示此警告。>这是由vee7引起的。 52我的计算机上有Net v1和2吗？我不知道它有多大可能。>如何在不删除版本1的情况下切换到版本2？不知道。
2019-10-22 11:17
我想知道数组的大小与RAM的可用性有关。如果我在主.c文件的任何函数之外分配一个数组，那么看起来我不能像我喜欢的那样大，所以我必须在512 UIT32上停止，否则我会在内存中产生内存不足的错误。但是如果我把数组移到函数中实际使用它的离子，我可以把它做成1024个没有问题。那么我怎么才能知道我能在多大程度上做到这一点呢？我的设备是PIC24FJ256GB206，具有96 KB的RAM，这意味着完整的第一页0x000—0x7FFF可用（除了第一个2K寄存器重叠的地方）。 以上来自于百度翻译 以下为原文 I am wondering about the size of arrays concerning RAM availability.If I assign an array outside any function in the main.c file then it seems like I cannot make it as big as I like, I had to stop at 512 UINT32 otherwise I got a memory shortage error on build.But if I move that array into the function that actually uses it, then I could make it 1024 without problems.So how can I find out how big I can make it at the most?My device is PIC24FJ256GB206 with 96 kB of RAM, which means the the full first page 0x000-0x7FFF is available (except the first 2K where registers overlap.How much of this is available for local function variables?
2019-04-03 14:51
这是一个严重的问题，阻碍了我们的发展。这已经到了我需要在代码改变之后重新启动我的电脑的地步。常规的固件编程似乎发生得很好，但是当我试图开始一个调试会话时，程序员挂起了。这就是我所看到的：我体验到这两个真正的冰和ICD3。我尝试从3.40升级到MPLAB X V3.45，但没有效果。我发现唯一可靠工作的解决方案是重新启动整个PC。在我修改代码的任何时候都会出现这种情况。这对我们来说是个大问题。 以上来自于百度翻译 以下为原文 This is a serious problem that is holding up our development. It has gotten to the point where I need to reboot my PC after any code change. Regular firmware programming seems to happen fine, but when I try to begin a debugging session, the programmer hangs. This is what I see: *****************************************************Connecting to MPLAB REAL ICE...Currently loaded firmware on REAL ICEFirmware Suite Version.....01.45.41Firmware type..............dsPIC33F/24F/24HTarget voltage detectedTarget device PIC24FJ256GB210 found.Device ID Revision = 0x4 I am experiencing this with both the Real ICE and the ICD3. I tried upgrading to MPLAB X v3.45 from 3.40 to no avail. The only solution I've found that works reliably is rebooting the whole PC. It seems to happen any time I modify the code. This is a big, big problem for us.
2019-06-17 10:45
你好我正在设计我的第一个斯巴达6 FPGA板。我对外部振荡器/时钟有几点怀疑。我浏览了时钟资源指南UG382，但它没有多大帮助，因为它主要描述了FPGA的内部电路，一旦你选择了振荡器就会出现。 Plz帮助我解决这些问题，以便我尽快结束这部分...1.在频率稳定性，负载电容和负载电流方面，xilinx spartan-6 FPGA的振荡器要求/规格有哪些。我试过但未找到XILINX评估套件中使用的振荡器的供应商。2.振荡器可以直接连接到FPGA引脚还是需要中间驱动器？在任何情况下，您可以给我一个链接，用于在将OScillator连接到FPGA之前使用的电路。3.我是否需要为FPGA的不同存储区设置不同的时钟/振荡器，或者连接到单个存储体的单个存储体/振荡器是否适用于所有存储体？4.是否建议使用FPGA的所有存储区？如果一家银行满足我们的要求;我们是否仍应向所有银行分配所需数量的IO。如果我们只使用一个银行..时钟应该送到同一家银行或其他银行。以上问题可能听起来很愚蠢，但我是初学者所以请和我一起喝啤酒。 P.S ..我已经通过UG382，但无法获得有关上述查询的任何帮助。非常感谢..以上来自于谷歌翻译以下为原文Hi I am designing my first spartan 6 FPGA board. I have few doubts related to external oscillator/clock. I went through clock resource guide UG382 but it wasnt of much help as it was mostlydescribing the inner circuitry of the FPGA, which comes once you have chosen your oscillator. Plz help me with these queries so thatI can wind up this part as soon as possible... 1. What are the requirement/ specifications of oscillator for a xilinx spartan-6 FPGA in terms of frequency stability, load capacitance and load current. I tried but failed to locate a supplier for the oscillators used in XILINX evaluation kits. 2. Can oscillator be directly connected to FPGA pins or we need an intermediate driver? In any case can you give me a link for a circuit used before connecting OScillator to FPGA. 3. Do I need to have different clocks/ oscillators for different banks of the FPGA or a single one connected to a single bank will do for all the banks? 4. Is it advised to use all the banks of the FPGA? If one bank fulfill our requirements; should we still distribute required number of IOs to all banks. If we use a single bank only.. should the clock be fed to the same bank or some other bank. Above questions may sound stupid but I am a beginner so please beer with me. P.S.. I have gone through UG382 but couldnt get any help regarding above queries. Thanx a lot..
2019-06-12 14:21
