先生/马姆，你可以告诉我如何在逻辑上连接或连接不同的逻辑块（在xilinx逻辑器中可用）？悲伤：以上来自于谷歌翻译以下为原文sir/mam, can u plz suggest me how do i interface or connect different logic blocks( available in xilinx logicore) in logicore?sad:
2019-02-12 10:58
你好，我给了一个10kHz的时钟到PSOC3套件的两个引脚：P1〔2〕和P3〔2〕。两者都被配置在“数字输出”引脚的示意图中……当我检查CRO上的输出时，我得到方波（如预期）…但是两个波的振幅是不同的……它对于P1（2）大约为3伏，对于P3（2）来说是4.4V左右。我........................ VDDD是3.3和VDDA 5。-----------------------------------------------------------------现在，HTTP://www. CyPress。DoCID＝42947。这个链接表明端口3应该被用作模拟，而端口1应该是数字的……所以这可以解释它……但我有“配置”为“数字输出引脚。那么为什么振幅不同呢？？？？ 以上来自于百度翻译 以下为原文 Hi there....I am giving a 10KHz clock to two pins of PSoC3 kit : P1[2] and P3[2]. Both have been configured in the schematic as "DIGITAL OUTPUT" pins...... When I check the output on a CRO, I get square waves [as expected] ...BUT the amplitude of both the waves is different.............it is around 3 volts for P1[2] and around 4.4volts for P3[2]. ........................my VDDD is 3.3 and VDDA is 5. ------------------------------------------------------------------------------------------------------------------- NOW, http://www.cypress.com/?docID=42947 This link suggests that Port 3 should be used as analog while Port 1as digital......SO this might explain it.............. But I have "configured" the pins as "DIGITAL" OUTPUT . So why varying amplitudes???
2019-01-15 06:39
我修改了AdCl微分器前置放大器项目，用PSoC 4 BLE先锋套件和附图中所示的加载单元工作。它最初工作，报告MVoT值在大约70（IIrc）和1024之间，这是最大值。然后我想做什么用redexcite和yellowexcite引脚反向ADC读数之间的激励电压的极性幻想，要减去反向极性测量从正常极性测量作为一种手段来有效的解决双。在没有得到那个工作，但是，我回到我之前保存在这个变更项目。问题是，现在第一个项目也不起作用。ADC值无变化时，传感器上的负载的变化。检查两个数字多用表，我可以看到，差分电压进入销bluesense和whitesense仍然变化始终与负载一如既往。测量out_1和out_2，之间的电压，但是，这应该是完全一样的是美联储的ADC，只读取0 V，偶尔漂流到0.1 mV。由于固件只计算到1 mV值，这mvolts总是等于previousvalue也被写入UART是有意义的。我炸了我的眼镜吗？幸运的是，我有一个包或两个在路上，但我想知道如果运算放大器，实际上，油炸，或是我有一些其他的错误在我的项目，我失踪。我可以分享其余的项目太多，如果能帮助。谢谢，Don。PSOG模式47.4 K 以上来自于百度翻译 以下为原文I modified the ADC_Differential_Preamplifer project to work with a PSoC 4 BLE Pioneer Kit and with a load cell as shown in the attached schematic. It worked initially, reporting mVolt values between about 70 (IIRC) and 1024, which is the maximum. I then tried to do something fancy by using the redExcite and yellowExcite pins to reverse the polarity of the excitation voltage between ADC readings, intending to subtract the reversed-polarity measurement from the normal-polarity measurement as a means to effectively double the resolution. After failing to get that to work, however, I returned to the project I saved before trying this change. The problem is, now the first project doesn't work either. The ADC is showing no change of values when the load on the sensor changes. Checking with two DMMs, I can see that the differential voltage going into pins blueSense and whiteSense still varies consistently versus load as it always has. Measuring the voltage between Out_1 and Out_2, however, which should be exactly the same as is being fed to the ADC, reads only 0 V, occasionally drifting to -0.1 mV. Since the firmware only calculates down to values of 1 mV, it makes sense that mVolts is always equal to previousValue so that nothing is being written to the UART. Did I fry my opamps? Fortunately, I have another kit or two on their way, but I would like to know if the opamps are, in fact, fried, or whether I have some other error in my project that I am missing. I can share the rest of the project too, if that will help. Thanks, Don. PSoC_Schem.png 47.4 K
2019-02-22 08:31
在我们的系统中，我们使用外部时钟源，频率为54MHz。我们希望获得133MHz的时钟，因此我们在DCM中使用以下方法：（54MHz * 22）/ 9 = 132MHz在用DCM提到上述处理之后，我想知道132MHz时钟的占空比是否为50％。或者，时钟的整个周期可能会有些偏差？以上来自于谷歌翻译以下为原文In our system, we use an external clock sourse, the frequency is 54MHz. We hope to get a 133MHz clock, so we use the following method with DCM:( 54MHz * 22 ) / 9 = 132MHz After such treatment mentioned above with DCM, I want to know if the duty cycle of the 132MHz clock is 50%. Or, the dutiy cycle of the clock maybe some deviations?
2019-01-25 09:03
