分析仪的输出PODS显示数据是否生成。问题是没有数据在FPGA上生成。当我通过示波器检查FPGA输入引脚上的信号时，会产生模式，但pk-to-pk电压为mV。当我将POD更改为2.5 V和1.8 V
2018-11-08 10:27
the pods. I am referenceing PNA Help A.10.25, but there is little info in there, and I can't find a
2018-10-15 11:12
boards have connectors' mark as 16962-61601) !As soon as PODs of 16962A and 16950B are organized
2018-09-21 11:35
sir, We are feeding input data to LSA through PODs and monitoring the output using Extractor tool.
2018-10-09 15:07
你好，我是Nikhil。我希望生成一些数字数据来测试我的比较器ASIC。我想使用模式生成器模块16720A生成序列/模式，并使用Agilent 16902逻辑分析器测试输出。我有以下问题：1）数据应该在10KHz左右，但模式发生器允许的最小速率只有1MHz。是否有可能以较低的费率生成数据？ 2）我想生成一个时钟和数据，最好是90度相移。该时钟用于馈送逻辑分析仪探头的时钟输入。我也可以这样做吗？ 3）我只能生成数据，但速率高达1MHz，但没有时钟输出选项。要测试此输出，我想使用逻辑分析仪探针。但我没有看到任何输出，可能是因为没有时钟并选择了错误的阈值电平。我不确定是否可以设置码型发生器输出电平，因此无法为逻辑分析仪设置合适的阈值电平。我使用示波器确认了模式发生器的数据输出。除数据速率部分外，它是正确的。我现在需要的只是探针的时钟输入，因此我需要使用模式生成器将其与数据一起生成。我需要以较低的费率生成数据。任何人都可以建议如何解决这些问题？如果我错过了可能需要的任何信息，请告诉我。此致，Nikhil 以上来自于谷歌翻译 以下为原文Hello, I am Nikhil. I wish to generate some digital data to test my comparator ASIC. I want to generate a sequence/ pattern using the pattern generator module 16720A and test the output using Agilent 16902 Logic Analyzer. I have the following problems: 1) The data should be at around 10KHz but the pattern generator allows a minimum rate of only 1MHz. Is it possible to generate data at lower rates? 2) I want to generate a clock along with the data, preferably with 90 degrees phase shift. This clock will be used to feed the clock input of the probe of logic analyzer. Can I do this as well? 3) I was able to generate only the data, but at high rate of 1MHz but there is no option for a clock output. To test this output, I want to use the Logic Analyzer probe. But I do not see any output, probably because of absence of clock and selecting wrong threshold levels. I am not sure if I can set the pattern generator output levels and thereby I cannot set the appropriate threshold level for Logic Analyzer. I confirmed the data output from pattern generator using an oscilloscope. It is correct except for the data rate part.All I need now is a clock input for my probe, thereby I need to generate it along with the data using the pattern generator. And I need to generate the data at lower rates. Can anyone please advise on how to get around these issues? Let me know if I missed out any information that maybe needed. Regards, Nikhil
2019-07-02 10:14
B4621A DDR总线解码器安装为16962A板和BGA插入器提供了一些默认配置。它是否可用于DDR3的默认配置，x16 32位（类似于DDR2，x16 32位，可用）???哪个BGA插入器必须用于32位和多少16962A板（2或3）？ DDR3 - 1600.我发现，B4621A设置中只包含16962A，DDR3 x16 16位默认配置。谢谢！ 以上来自于谷歌翻译 以下为原文B4621A DDR bus decoder installation provides some default configurations for 16962A board and BGA interposers. Is it available a default config for DDR3, x16 32bit (similar to DDR2, x16 32bit, which is available) ??? Which BGA interposers have to be used for 32bit and how many 16962A boards (2 or 3) ?? DDR3 - 1600. I found, there is only 16962A, DDR3 x16 16bit default config is included to B4621A setup. Thank you!
2018-09-26 14:47
大家好，我正在使用带SPC5 Studio的SPC560C50L3 MCU。我正在尝试添加一个库文件，该文件使用大量堆栈和堆使用动态分配到我的应用程序中。由于堆栈溢出，我的代码常常陷入其中。现在我可以在user.ld文件中更改堆栈大小。但是如何在运行时检查堆栈和堆使用情况？任何建议都会有所帮助。问候THOMAS。 #spc560＃stack-overflow以上来自于谷歌翻译以下为原文 Hello Everyone,I am working on SPC560C50L3 MCU with SPC5 Studio. I am trying to add a library file which uses heavy stack and heap using dynamic allocations into my application. My code used to stuck in between due to stack overflow. Now I am able to change the stack size in the user.ld file. But how do I check the stack and heap usage at run time ? Any suggestion would be helpful.RegardsTHOMAS. #spc560 #stack-overflow
2019-01-25 14:16
嗨，大家好，有PSOC3和/或PSoC5的模拟器吗？模拟代码和组件的东西？雨果 以上来自于百度翻译 以下为原文Hi all, Is there a simulator for the PSoC3 and/or PSoC5 ? Something which simulates the code and components? Hugo
2019-07-26 08:02
嗨，由于我对分析仪和这些仪器本身的使用非常陌生，我在尝试根据我的要求探测信号时有点迷失。我有16803A逻辑分析仪。我的要求是：while（1）{if（EOC信号从高到低转换）在那个时刻采样数据{Dont sample wait for trigger}}触发事件定期发生，数据需要采样仅在EOC信号的下降沿而不是连续的。这就是我设置的触发条件：i）如果总线/信号EOC下降沿连续发生1次则触发和填充存储器采样条件异步采样1）采样选项：全通道，500 Mhz 2）采样周期：2ns 3）采集深度：1M 50％Poststrore但是发生的猜测是，它在第一个触发事件（从EOC的高到低）捕获数据并继续永久捕获直到我停止。但是我的EOC信号产生从低到高的交易，我期待停止捕获数据。 1）触发和填充内存是否会填满整个1 M空间？ 2）当EOC低或低到高时，如何停止采样？有人可以建议我解决这个问题吗？请原谅我的无知。干杯sivan 以上来自于谷歌翻译 以下为原文Hi, As i am very much new to the usage of analyzers and such instruments themselves, i am a bit lost in trying to probe the signals as per my requirement.I have 16803A logic Analyzer.My requirement is: while(1) { if( EOC signal make a high to low transition) sample the data at that instant else { Dont sample wait for the trigger } } The trigger event occurs at regular intervals, and data needs to be sampled only at the falling edge ofEOC signal and not continuously. This is what thetrigger condition i had set: i) Ifbus/signal EOC falling edge occurs1 consecutively then Trigger and fill memory Sampling condititions Asynchronous sampling 1) Sampling options:Full channel,500 Mhz 2) Sampling period : 2ns3) Acquisition depth : 1M 50% Poststrore But what guess happening is that, it captures data at the first trigger event ( high to low of EOC) and continues capturing forever till i stop.But my EOC signal makes a low to high transaction at which i expect to stop capturing data. 1) Will trigger and fill memory will fill entire 1 M space ? 2) How do i stop sampling when the EOC is low or at low to high ? Can anyone suggestme a solution on this please? Please forgive my ignorance. Cheers sivan
2018-12-11 15:56
SOPC中的Avalon总线是什么？Nios II系统中的紧耦合存储器该如何去设计？怎样去设计一种SRAM的接口？
2021-05-28 06:44
