你好，我目前正处于Spartan 3E PQ208的存储器接口设计中。我意识到这是非常雄心勃勃的，因为我之前没有设计过带有FPGA的电路板，但是我目前正在研究几个参考原理图来帮助我完成这个过程。我正在尝试优化IO引脚，从数据表中我了解到有几个IP引脚只是输入。 DDR SDRAM在输出端口方面没有多少，但我想尽可能使用IP引脚。目前我的原理图中有一个DVI接收器IC，它部分地与IP引脚相连。在与IP引脚接口时是否应该考虑特殊注意事项？或者将DDR SDRAM连接到Spartan 3E的具体要求是什么？到目前为止我的考虑： -Bank＃需要具有相同的逻辑电平 - 需要考虑高速布局 - > 165MHz，4层PCB上具有匹配长度的并行总线（学生预算） - 由于资源而使用的PQ208封装 - 无法访问BGA焊接设备 - 用于DVI Rx接口的Bank0，用于2 x DDR SDRAM的Bank1和Bank2（Qimonda HYB25D512160CE-5） - 剩余的IO引脚将直接映射到另一个Spartan 3E PQ208 - 频率合成器也将接口任何意见或建议将不胜感激。提前致谢， -Dex以上来自于谷歌翻译以下为原文Hello, I'm currently in the middle of a memory interface design for a Spartan 3E PQ208. I realise that it quite ambitious given that I have not designed a board with a FPGA before, however I am currently looking at several reference schematics to help me with the process. I am trying to optimize for IO pins, and from the datasheet I understand that there are several IP pins that are input only. DDR SDRAM does not have much in the ways of output only ports but I would like to use IP pins whenever possible. Currently I have a DVI Receiver IC in my schematic that is partially tied to IP pins. Are there special considerations that I should take into account when interfacing to the IP pins? Or specific requirements for interfacing DDR SDRAM to a Spartan 3E? My considerations so far:- Bank# needs to have the same logic level - high speed layout needs to be taken into account - >165MHz, parallel bus lines with matched length on a 4 layer PCB (student budget) - the PQ208 package used due to resources - no access to equipment for BGA soldering - Bank0 for DVI Rx interface, Bank1 and Bank2 for 2 x DDR SDRAM (Qimonda HYB25D512160CE-5)- The remaining IO pins will be mapped directly to another Spartan 3E PQ208- A frequency synthesizer will be interfaced as well Any comments or advice would be greatly appreciated. Thanks in advance,- Dex
2019-05-10 13:59
