我看一款AD的数据手册16位的，但是有一个参数是 no missing codes (NMC)是14位，另一个参数是有效位数ENOB是13.3位,我知道ENOB是在高频中需要经过SINAD算出
2018-10-29 09:10
您好Xilinx社区，我对使用SmartXplorer方法试图改善设计时间感兴趣。我似乎能够在命令行工具上找到大量信息，并且我了解如何从命令行运行程序等。但是，我似乎无法找到的是如何在XPS项目中使用此工具。我似乎无法在SmartXplorer下运行一个通用的BSB Wizard项目。任何人都可以了解如何做到这一点？提前致谢。以上来自于谷歌翻译以下为原文Hello Xilinx Community, I'm interested on using the SmartXplorer method to try to improve the timing of my design. I seem to be able to find lots of information on the command-line tools, and I understand how to run the program, etc. from the command line. However, what I can't seem to find is how to use this tool on an XPS project. I can't seem to even get a generic BSB Wizard project to run under SmartXplorer. Can anyone shed some light on how to do this? Thanks in advance.
2018-10-17 14:14
大家好，我正在接受错误，而我正在设计中。我现在正在测试hardmacro。 hardmacro由一个环形振荡器和计数器组成。在设计中，我唯一要做的就是实例化hardmacro。在合成的PAR部分，我得到了致命错误。我在谷歌搜索，但我找不到任何关于该错误。FATAL_ERROR：Par：pwr_task.c：72：1.2- 未处理的Pds例外有关此问题的技术支持，请访问谢谢以上来自于谷歌翻译以下为原文Hi all, I am receving below error, while I am sythesizing the design. I am now in the process of testing the hardmacro. The hardmacro is consist of one ring oscillator and counter. In the desing only thing that I do is to instantiate the hardmacro. In the PAR part of the synthesize I got below fatal error. I searched in google but I could not find anything about that error. FATAL_ERROR:Par:pwr_task.c:72:1.2 - Unhandled Pds exceptionFor technical support on this issue, please visit thanks
2019-07-15 14:52
:\\\\Users\\\\omar.wolfe-hussein\\\\Documents\\\\Apollo\\\\NXP-WIN-IMX8\\\\IoTEntOnNXP\\\\drivers\\\\CAN_NMC
2023-05-17 07:42
:\\\\Users\\\\omar.wolfe-hussein\\\\Documents\\\\Apollo\\\\NXP-WIN-IMX8\\\\IoTEntOnNXP\\\\drivers\\\\CAN_NMC
2023-05-05 14:12
其使用仍然相当普遍。LiFePO4（简称磷酸盐）和现有锂—镍—锰—钴 (NMC) 等替代性化学物质已经针对需要更高速率的各种应用进行了优化，但也可以作为折衷方案，针对能量（容量）进行优化。锂离子
2018-09-20 16:21
我正在开发一个部分重新配置的项目，它使用总线宏（我知道它们已被弃用;但它是项目使用的内容并且更改会使项目陷入困境）。问题是如果总线宏没有连接任何输出，则ISE Map（12.1）会抛出错误。ISE无法识别信号的“保存”属性（属性s：字符串; dummy_output的属性：信号为“是”;）我已尝试使用AR＃30112中建议的解决方案但没有成功（也许我没有正确解释）。是否有任何解决方案不涉及禁用“修剪未使用的逻辑”，也不添加大量的虚拟逻辑和输出信号？以上来自于谷歌翻译以下为原文I'm working on a project on partial reconfiguration which uses bus macros (I know they're deprecated; but it's what the project uses and changing that would mess up the project too much). The problem is thatIf a bus macro doesn't have any output connected, ISE Map (12.1) throws an error.ISE doesn't recognize "save" attributes for signals (attribute s: string; attribute s of dummy_output: signal is "yes"; )I have tried with the solution suggested in AR #30112 with no success (maybe I haven't interpreted it right). Is there any solution that does not involve disabling "trim unused logic" nor adding lots of dummy logic and output signals?
2018-10-08 11:15
程序（语言环境通常会导致奇怪的错误）什么工作：运行fpga_editor filename.nmc在“硬宏”字段上写入文件的完整路径，而不是单击“浏览...”通常在另一个Xilinx程序（EDK，ISE
2018-10-19 14:40
请问单片机如何控制AD7766采集ADC信号？
2021-11-18 07:13
FPGA应用设计中一种崭新的硬宏开发流程是怎样的
2021-05-06 06:49
