the up state maching going trough the right states(exept for the failing run) so there mush have
2018-12-13 16:57
存储器控制器用户指南列出了数据，地址，控制和时钟信号的长度匹配要求。给出的数字是否必须补偿FPGA和DDR2封装内的键合线长度？如果是这样，我在哪里可以找到这些长度？谢谢，TL以上来自于谷歌翻译以下为原文The memory controller user guide lists length matching requirements for the data, address, control, and clock signals.Do the numbers given have to be compensated for bonding wire lengths inside the FPGA and DDR2 packages?If so, where do I find those lengths? Thanks,TL
2019-03-15 10:06
