\n");#endif#if defined(CONFIG_LMB)puts("CONFIG_LMB\n");#endif#if IMAGE_ENABLE_OF_LIBFDT
2019-09-18 05:45
你好，我正在尝试做一个简单的显示应用程序来测试Virtex-4 VSK上的LCD。此应用程序在16x2 LCD上显示单行文本。除了micrlaze，bram / bram ctrls，lmb
2020-06-02 06:59
lmb_bram_if_cntlr PARAMETER INSTANCE = dlmb_cntlr_0 PARAMETER HW_VER = 2.10.a PARAMETER C_BASEADDR
2019-11-05 09:53
我正在使用Atlys spartan 6 xc6slx45。我正在使用双处理器系统。我创建了2个项目，其中一个包含microblaze0的代码，其他包含microblaze1的代码。当我运行代码时出现此错误：无法连接microblaze。指定的处理器编号无效.processor（2）不存在。以上来自于谷歌翻译以下为原文I'm using Atlys spartan 6 xc6slx45.I'm using dual processor system.I created 2 projects one contain a code of microblaze0 and other contain the code of microblaze1.When I run the code I got this error :Unable to connect microblaze.Invalid processor number specified.processor(2) does not exist.
2019-07-30 07:13
我有一个带有64kb BRAM的Microblaze，带有指令和数据空间（一个端口上的标准I和另一个端口上的D）。我有另一个64kb只在一个端口上连接到Microblaze并且只包含数据。第二个端口将由自定义VHDL代码写入。第二个BRAM地址在Microblaze上为0x00010000。在导出BRAM的第二个端口以供自定义VHDL代码使用之后，我对VHDL端的BRAM地址感到有些困惑。 BRAM的第一个位置是VHDL侧0x00000000吗？还是0x00010000？在我看来，VHDL方面不知道如何在MicroBlaze端配置BRAM。我也意识到（至少我认为是这种情况）是64kb BRAM是几个物理BRAM。本地内存总线控制器似乎通过将内存请求映射到正确的BRAM来处理这个问题。但是，VHDL方面并不清楚（我怀疑它不是这样）。您是否必须在VHDL端处理单个物理BRAM。提前致谢，BB以上来自于谷歌翻译以下为原文I have a Microblaze with 64kb BRAM with instruction and data space (standard I on one port and D on the other port).I have another 64kb that is only connected to the Microblaze on one port and will only contain data.The second port will be written to by custom VHDL code.The second BRAM address is at 0x00010000 on the Microblaze.After exporting the second port of the BRAM to be used by the custom VHDL code, I'm a bit confused as to the address of the BRAM on the VHDL side.Is the first location of the BRAM on the VHDL side 0x00000000?or is it 0x00010000?It seems to me that the VHDL side doesn't know about how the BRAM is configured on the MicroBlaze side.I also realize (at least I think this is the case) is that the 64kb BRAM is actaully several physical BRAMs.The local memory bus controller seems to take care of this by mapping memory requests to the correct BRAM.However, it's not clear how (and I suspect that it isn't) on the VHDL side.Do you have to deal with individual physical BRAMs on the VHDL side. Thanks in advance,bb
2019-03-04 12:09
我有通过PlanAhead生成的MicroBlaze设计。我想将VHDL逻辑连接到XPS中生成的BRAM。 MicroBlaze将通过本地存储器总线访问一个端口，将第二个端口访问VHDL。编写VHDL代码，但我不确定如何实例化我的VHDL代码。 PlanAhead有一个顶级模块，称为system_stub.v，它包含MicroBlaze的实例化。如何实例化我的VHDL模块（bram.vhd）？它是否在system_stub.v文件中实例化？或者别的地方？提前致谢。BB以上来自于谷歌翻译以下为原文I have a MicroBlaze design generated via PlanAhead.I want to connect VHDL logic to a BRAM generated in XPS.The MicroBlaze will access one port via the local memory bus and the second port to VHDL.The VHDL code is written, but I'm not sure how to instantiate my VHDL code.PlanAhead has a top level module which is called system_stub.v which contains the instantiation of the MicroBlaze.How do I instantiate my VHDL module (bram.vhd)?Is it instantiated in the system_stub.v file? or somewhere else? Thanks in advance. bb
2019-03-05 13:31
请问一下怎么在SoPC上实现波形发生器的设计？
2021-05-06 07:01
如何在SoPC上实现的波形发生器？
2021-04-27 06:50
本文采用FPGA 和MicroBlaze 进行嵌入式系统设计，文中在分析了FFT算法后，描述了运算的蝶形单元，地址生成单元及FFT的实现过程。从实际设计出发，完成了基于FPGA的单精度浮点运算器的FFT设计，精度达到10-6。大大缩小了接收机体积，便于系统实现小型化、集成化。捕获及跳频同步等算法采用硬件实现，加快了捕获跟踪速度。实验结果表明FPGA系统设计是正确可行的。
2021-02-22 07:36
MicroBlaze的体系结构是怎样构成的？MicroBlaze嵌入式开发工具EDK有什么功能？MicrOBlaze与液晶显示模块的接口怎样去设计？
2021-04-28 07:21
