is not needed.) Can I say that the JTAG level for 7K325TFF990 in my Design is jut 3.3v , not 1.8v? In my opinion
2019-03-20 15:43
你好。我需要帮助我的toshiba windows 10笔记本电脑。当安装了3gb vram时，我的vram显示为32mb。在驱动程序更新后，我安装的vram下降到1.7 gb，专用的vram为32mb。视频卡是intel hd图形，我看到其他人通过从Windows 10通过uefi（启动）访问BIOS报告相同的问题。启动无法访问，因此无法修复此错误。以上来自于谷歌翻译以下为原文hello. i need help with my toshiba windows 10 laptop.my vram is show 32mb when 3gb vram was installed. after a driver update my installed vram dropped to 1.7 gb with the dedicated vram of 32mb. the video card is intel hd graphics, and i have seen other persons report the same problem by accessing bios through uefi(boot) from windows 10. the boot is not accessible, so there is no way of fix this error.
2018-10-25 15:00
我正致力于Virtex-6设计的时序收敛（使用ISE 14.7）。我面临着一个奇怪的问题，ISE显然将一些完全不相关的逻辑合并在一起（信号甚至不在相同的时钟频率上运行）。我已经设置了以下选项（适用于Synthesis和MAP / PAR），以避免优化不相关的信号： -resource_sharing off -ignore_keep_hierarchy off -LUT结合起来MAP和Synthesis的Optmization设置为“Speed”。-keep_hierarchy设置为“Soft”，-hetlist_hierarchy设置为“Rebuilt”。我厌倦了-keep_hierarchy“是”的合成，但如果我这样做，我会遇到大量的映射器错误消息。附上你可以找到时间报告。失败路径在11954行。信号“../fmc_raw_dat_dff_s”与所有“../inst_tmem_user/ ..”信号位于不同的时钟域上，并且它们不必彼此做任何事情。 “../inst_tmem_user / ..”中的信号与配置寄存器组相关，“fmc_raw_dat_dff_s”信号是ADC输入后直接与寄存器组无连接的流水线级（它不可配置且具有没有来自寄存器库或类似物的运行时钟启用）。这条道路上的可疑网名如“lut77809_42134”也引起了我的注意。没有使用“人类可读”名称这一事实指出该工具将不同的逻辑优化在一起，因此它无法分配可读的名称（因为我的VHDL源中没有这样的信号）。有人知道这个（或类似的）问题吗？有什么建议我可以试试吗？以上来自于谷歌翻译以下为原文I am working on timing-closure for a Virtex-6 Design (using ISE 14.7). I am facing the strange issue that ISE is obviously merging some logic together that is completely unrelated (the signals do not even run on the same clock frequency). I already set the following options (for Synthesis and MAP/PAR where applicable) to avoid optimization of signals that are not related:- resource_sharing off- ignore_keep_hierarchy off- LUT Combining off Optmization of MAP and Synthesis is set to "Speed".-keep_hierarchy is set to "Soft" and -hetlist_hierarchy to "Rebuilt". I tired synthesyzing with -keep_hierarchy "Yes" but I run into tons of mapper error messages if I do so. Attached you can find the timing report. The failing path is on line 11954. The signal "../fmc_raw_dat_dff_s" is on a different clock domain than all the "../inst_tmem_user/.." signals and they do not have to do anything with each other. The signals in "../inst_tmem_user/.." are related to the register bank for configuration, the "fmc_raw_dat_dff_s" signal is a pipeline stage directly after the ADC input that has no connections to the register bank (it is not configurable and has no runtime-clock enable from the register bank or anything similar). The suspicious net-names like "lut77809_42134" for this path also catched my attention. The fact that no "human readable" names are used points into the directon that the tool optimizes different logic together and hence it cannot assign a readable name (because no such signal is present in my VHDL sources). Does anybody know this (or a similar) problem? Any suggestions what I could try?
2018-11-09 11:41
大家好，我用的是PI32MZ，它连接到带有SPI接口的LTC1864ADC转换器。我检查了我的SCKL引脚，但没有脉冲。似乎spi不是活动的.任何想法都会被理解.int main(void){CFGCONbits.JTAGEN=0;TRISA=0xC000TRISA=0xC000TRISB=0;TRISA=TRISA=0;TRISA=TRISA=0xC000TRISB=0;TRISC=TRISB=0;TRISA=TRISC 0;TRISC=0;TRISC 0;TRISC=0;TRISC 0;TRISC 0;TRISC=0;TRISC 0;TRISC=0;TRISC=0;TRISC 0;TRISC 0;TRISC 0;TRISC 0;TRISC 0/PMRDTRITRITRISC比特TRITRITRITRITRITRITRISC比特TRITRITRITRITRITRITRITRITRITRISC比特TRITRITRITRITRITRISC比特TRITRISC14=0;TRISC13=0；//sosciTRISGbits.TRISGbits.TRISG0=1；//sdi4TRITRISB比特.TRISB1=1；//sdi4TRITRITRISB比特.TRISB1=1=0；//sdi4TRISD14141414TRISD比特.TRISD10=0；//ck4CNPUDCDCDCDCDCDCDCDCDCD钻比特.CNPUD0=0；//sckkk4CNPUD位CNPUD位.CNPUD位.CNPUD10=0，//0=0=0=0=0=上拉式禁用CNPUBBB位被上拉禁用CNPUBCNPUG比特.CNPUB1=0=0；//0=//0=上拉ANSELC=0X0000;ANSANSELF=0X0000;ANSELF=0X0000;ANSELF=0X0000;ANSELG=0X0000;ANSELG=0X0000;CFGCON比特.IOLOCK=0;CFGCON比特.CFGCON比特.IOLOCK=0;CFGCON比特.PMDLOCK=0;CFGCON比特.PGLOCK=0;CFGCON比特.PGLOCK=0;CFGCON比特.PGLOCK=0;SDI4R=0;SDI4R=0b1100；//RG0;SDI4R=000b1100；//RG0，SDI4_asm_asm_uu_asm_us.SPI4EIE=0；//禁用所有中断IEC5bit。SPI4TXIE=0；//di所有可中断SPI4CON=0；//停止并重置SPI1.rData=SPI4BUF；//停止并重置SPI1.rData=SPI4BUF；//清除接收缓冲区IFS5bits接收缓冲区IFS5bits接收缓冲区IFS5bitsSPI4RXIF=0；//清除任何现有的eventIPC4141比特.SPI41bits.SPI4RXIP=0；//清除优先级IPC41bits.SPI4RXIP.SPI4RXIP=0；//清除优先级IPC41bits优先级IPC41bits优先级IPC41bitsSPI4RXIP=3.SPI4RXIP=3；///优先级IPC41IPC41404040404040404040404041bitsIPC41bitsIPC41能干的RX，TX和错误中断SPI4BRG=0x1；//使用FPB/4时钟频率SPI4STAT位.SPIROV=0；//清除溢出SPI4CON=0x0000D620；//SPI开启，清除溢出SPI4CON=0x0000D620；//SPI开启，禁用sdo pin，16位传输，主控PBCLK2，Mssen禁用///u asm_u volatil("ei")；(1){LATBbit.LATB1=1;//APP_StartCoreTimer(0)；//APP_CoreTimer_Del延迟(300)；延迟(18)；LATB位.LATB位.LATB1=0；//LATB1=0；//同时(计数< 16计数；16)；int数据；//读取SPI数据缓冲SPI数据缓冲器数据=SPI数据缓冲器数据=SPI4BUUF；}}void_u.u.((中断(ipl3SRS)，矢量(_SPI4_SPI4_RX_VECTOR))(矢量(_SPI4_SPI4_RX_RX_RX_VECTOR))))(矢量((_SPI4_SPI4_SPI4_RX_RX_RX_/使用在此接收的数据NT数据；//Read SPI数据BuffelDATa= SPI4BUF；/ /清除RX中断FraveS5BITS；SPI4RXIF＝0；}
2019-10-22 06:19
