我正在使用ODDR2生成外部时钟（ISE = 13.1，Planahead = 13.1）：clk5m_inst：ODDR2通用映射（DDR_ALIGNMENT =>“NONE”， - 将输出对齐设置为“NONE”，“C0”，“C1”INIT =>'0'， - 将Q输出的初始状态设置为“0”或'1'SRTYPE =>“SYNC” - 指定“SYNC”或“ASYNC”设置/复位）端口映射（Q => clk_alc， -1位输出数据C0 => clk5m， -1位时钟输入C1 =>不（clk5m）， -1位时钟输入CE => n_enable_clock， -1位时钟使能输入D0 =>'0'， -1位数据输入（与C0相关）D1 = >'1'， -1位数据输入（与C1相关）R =>复位， -1位复位输入S =>'0' -1位置位输入）;但是当我尝试将Q输出与Planahead程序连接时，我得到了以下消息：“由OLOGIC_X12Y33.OSRUSED.OUT驱动的物理连接的冲突网络：U_0 ............. GROUND”在原始ODDR2中，SET和RESET是2个输入引脚，但是Planahead将它们视为1个引脚。我能做什么？我可以在没有Planahead的情况下将这个FPGA引脚放在ucf文件上并且没有问题吗？谢谢熔点以上来自于谷歌翻译以下为原文I'm using ODDR2 to generate an external clock (ISE = 13.1, Planahead = 13.1): clk5m_inst : ODDR2generic map (DDR_ALIGNMENT => "NONE",-- Sets output alignment to "NONE","C0", "C1" INIT => '0',-- Sets initial state of the Q output to '0' or '1'SRTYPE => "SYNC" -- Specifies "SYNC" or "ASYNC" set/reset )port map (Q => clk_alc,-- 1-bit output dataC0 => clk5m,-- 1-bit clock inputC1 => not(clk5m), -- 1-bit clock inputCE => n_enable_clock, -- 1-bit clock enable inputD0 => '0',-- 1-bit data input (associated with C0)D1 => '1',-- 1-bit data input (associated with C1)R => reset,-- 1-bit reset inputS => '0' -- 1-bit set input); But when i try to connect the Q output with Planahead program I have the message:"Conflicting nets for physical connection driven by OLOGIC_X12Y33.OSRUSED.OUT: U_0............. GROUND" In the primitive ODDR2, SET and RESET are 2 input pins, but Planahead sees them as 1 pin.What can I do?Can I place on ucf file this FPGA pin without Planahead and without problems?Thanksmp
2019-06-17 14:43
