) Recognized 2 FSMs in module "Receive_Print_Datas(fast)".# # Loading D:/modeltech64_10.2c
2016-01-14 10:52
大家好，我已经读过每个vhd文件应该只有一个状态机，因此可以整齐地完成合成。我的问题是，我们可以在一台状态机中拥有多个独立的进程吗？或者这是否会导致实施程序中出现无法预测的错误？简而言之，我可以使用单个状态机但多个独立进程的vhd文件吗？谢谢以上来自于谷歌翻译以下为原文Hello guys,I have read that there should be only one state machine per vhd file, so that synthesis can be done neatly. My question is that, can we have multiple independent processes in a single state machine? Or does this lead to un-predictable bugs in implemented program?Briefly, can I have a vhd file with a single state machine but multiple independent processes?Thanks
2019-02-21 11:03
大家好我们必须写一个vhdl解码器代码解码器特别是用状态机构建我们怎么知道对于一个FPGA的好工作有多少状态（例如virtex5 FX100t）？谢谢你的回答沙洛姆以上来自于谷歌翻译以下为原文Hello Everybody We have to write a vhdl decoder code The decoder is especially built with state machineHow can we know what is the number of states that is limit for the good work of one FPGA (e.g virtex5 FX100t) ?? thanks for any answersShalom
2019-01-17 09:18
嗨，大家好正如我在标题中所说，我有两个有限状态机，其中一个将多次运行另一个（现在是两个）。计划具有从1到第2 FSM的信号，直到它到达初始状态为止。然后初始状态将驱动“标志”信号0.然后第一个FSM将进入第二个状态并再次运行第二个FSM。最后两者都将回到初始状态，直到另一个标志启动第一个“控制器”FSM。我观察到的是第二次只运行一次。我可以看到标志变为1然后是0.所以我认为它正在工作但是一次。提前致谢以上来自于谷歌翻译以下为原文Hi guys As I said in the title I have two finite state machines and one of them will run the other multiple times (it is two for now). Plan is having a signal which is 1 through the 2nd FSM until it arrives to initial state back. Then initial state will drive the "flag" signal 0. Then the first FSM will go to the second state and run the 2nd FSM once more.In the end both will be back to the initial state until another flag start the first "controller" FSM. What I observed is second one runs only for once. I can see the flag becomes 1 and then 0. So I thought it is working but for once. Thanks in advance
2018-11-01 16:15
您好我试图在aspratan6中实现此代码我无法理解为什么它永远不会完成合成过程，我明白这是很多路由要完成但它甚至无法完成SYNTHESIS。这个代码在isim上工作，它完全符合我的预期。我实例化的处理元素是一个8位XOR.entity dicionario isPort（sys_clk：在STD_LOGIC中; sys_rst：在STD_LOGIC中; word：在STD_LOGIC_VECTOR中） （7 downto 0）; valid_word：在STD_LOGIC; symbol_out：out std_logic_vector（23 downto 0））; end dicionario;架构行为的dicionario istype arr是std_logic_vector的数组（0到2047）（7 downto 0）;类型symbol_arr是数组（0到255）std_logic_vector（7 downto 0）;类型sm_t是（WAIT_START，COUNT_WORDS，PRIORITY_ENCODER）;-sinais做dicionariosignal匹配：std_logic_vector（2047 downto 0）;信号old_match：std_logic_vector（2047 downto 0）;信号search_buff ：std_logic_vector（2047 downto 0）;信号lookahead_buff：std_logic_vector（63 downto 0）;信号past_words：std_logic_vector（2047 downto 0）;信号符号：std_logic_vector（23 downto 0）;信号word_counter：自然范围0到2048;信号done_reg： std_logic;信号word_reg：std_logic_vecto r（7 downto 0）;信号symbol_vector：symbol_arr;信号word_vector：arr;信号状态：sm_t;信号set_reg：std_logic;信号info_pack：std_logic_vector（31 downto 0）;常数零：std_logic_vector（2047 downto 0）：=（其他=>'0'）;常量：std_logic_vector（2047 downto 0）：=（其他=>'1'）; COMPONENT processing_elementPORT（sys_clk：IN std_logic; sys_rst：IN std_logic; set：IN std_logic; x：IN std_logic_vector（ 7 downto 0）; y：IN std_logic_vector（7 downto 0）; match：OUT std_logic）; END COMPONENT; startsymbol_out processing_element_for：for 0 in 0到2047 generateInst_processing_element：processing_element PORT MAP（sys_clk => sys_clk，sys_rst => sys_rst，set => set_reg，x => word，y => word_vector（2047-i），match => match（2047-i））; end generate processing_element_for; process（sys_clk）beginif rising_edge（sys_clk）thenif sys_rst ='1'setset_reg done_reg symbol'0'）; state old_match'0'）; elsecase state iswhen WAIT_START => if valid_word ='1'soset_reg if（（match / = zeroes）and（matc h / = 1））thenword_counter state end if; end if;当COUNT_WORDS => if valid_word ='1'soleword_counter end if; if match = zeroes thenset_reg symbol word_counter state elseold_match end if; end case; end if; end if; end进程;-SHIFT REGISTERprocess（sys_clk）beginif rising_edge（sys_clk）thenif sys_rst ='1'henword_reg'0'）; for 0 in 0 to 2047 loopword_vector（i）'0'）; end loop; elseif valid_word ='1' thenword_reg word_vector（2047）for i in 0 to 2046 loopword_vector（2047-i-1）end loop; end if; end if; end if; end process; end Behavioral;以上来自于谷歌翻译以下为原文Hello i am trying to implement this code in a spratan6 I can't understand why it never finishes the synthesis process, i do understand that it's a lot of routing to be done but it can't even finish SYNTHESIS. And this code does work at the isim, it does exactly what i expect it to do.The processing element which i am instantiating is an 8 bits XOR.entity dicionario isPort ( sys_clk : in STD_LOGIC;sys_rst : in STD_LOGIC;word : in STD_LOGIC_VECTOR(7 downto 0);valid_word : in STD_LOGIC;symbol_out : out std_logic_vector(23 downto 0));end dicionario;architecture Behavioral of dicionario istype arr is array(0 to 2047) of std_logic_vector(7 downto 0);type symbol_arr is array(0 to 255) of std_logic_vector(7 downto 0);type sm_t is (WAIT_START, COUNT_WORDS, PRIORITY_ENCODER);-- sinais do dicionariosignal match : std_logic_vector(2047 downto 0);signal old_match : std_logic_vector(2047 downto 0);signal search_buff : std_logic_vector(2047 downto 0);signal lookahead_buff : std_logic_vector(63 downto 0);signal past_words : std_logic_vector(2047 downto 0);signal symbol : std_logic_vector(23 downto 0);signal word_counter : natural range 0 to 2048;signal done_reg : std_logic;signal word_reg : std_logic_vector(7 downto 0);signal symbol_vector : symbol_arr;signal word_vector : arr;signal state : sm_t;signal set_reg : std_logic;signal info_pack : std_logic_vector ( 31 downto 0);constant zeroes : std_logic_vector(2047 downto 0) := (others => '0');constant ones : std_logic_vector(2047 downto 0) := (others => '1');COMPONENT processing_elementPORT(sys_clk : IN std_logic;sys_rst : IN std_logic;set : IN std_logic;x : IN std_logic_vector(7 downto 0);y : IN std_logic_vector(7 downto 0); match : OUT std_logic);END COMPONENT;beginsymbol_outsys_clk,sys_rst => sys_rst,set => set_reg,x => word,y => word_vector(2047-i),match => match(2047-i));end generate processing_element_for;process(sys_clk)beginif rising_edge(sys_clk) thenif sys_rst = '1' thenset_reg
2019-02-22 08:09
我正在寻找一个更好的，即更低的传播延迟，来做到这一点：pixel_outpx0到px31是4位整数（值0到15）。我只需要第一个不为零的px值。上面的代码有效，但超出了我的时间限制（出于显而易见的原因）。我并不十分关心节省空间，因为我在FPGA中仍有足够的空间，即我宁愿拥有更快的电路来占用更多的空间。在使用VHDL描述它们之前，我一直在尝试使用分立元件来研究我的电路，但是在这种情况下我无法想出一个电路，而且我不完全确定这个代码产生了什么。 32个比较器可以提供32比1多路复用器吗？但是在那里有“其他”，我觉得如果不等待信号传播通过至少31个门，最终结果就无法解决？我开始认为我需要一个优先电路来提供多路复用器或类似的东西，但我无法弄清楚逻辑。任何见解将不胜感激。谢谢，马修以上来自于谷歌翻译以下为原文I'm looking for a better, i.e. lower propagation delay, to do this: pixel_out
2019-01-17 10:44
假设我有一个设计，其中每个最后的BEL都定位到固定位置，因此放置器基本上没有自由度。问题：改变成本表会影响路由器的行为吗？为了记录，我正在使用大约95％固定位置的设计，因此更改成本表肯定会影响我的设计。最后5％的位置很好，但是我从路由器得到了一些不理想的结果 - 它在LOC'd单元之间做了一些愚蠢的事情路由路径。我想知道是否值得花时间在Amazon EC2上购买所有100个成本表的详尽探索。不幸的是，现在我无法判断更改成本表是否会影响路由器，因为它正在改变最后5％的位置（对LOC'd区域的拥塞产生“连锁反应”）或是否更改成本表实际上导致路由器行为明显不同。在后一种情况下，尝试所有100个表格对我来说可能是值得的。PS：设备是Spartan-6，它放置在地图阶段，所以我在这里添加了成本表标志。我假设成本表选择被隐藏在ncd的某处，以便路由器可以检索它...PPS：这是一个疯狂密集的设计;如果没有放置限制，它甚至不会以10mhz路由。因此，我可能在par工具的预期使用模型之外运行。以上来自于谷歌翻译以下为原文Suppose I have a design in which every last BEL is LOC'd to a fixed location, so that the placer has essentially zero freedom. Question: will changing the cost table influence the behavior of the router? For the record, I am working with a design that is about 95% fixed-placement, so changing the cost table definitely affects my design.The placement of the last 5% is just fine, but I'm getting some suboptimal results from the router -- it's doing some kind of dumb things routing paths between LOC'd cells.I'd like to know if it's worth buying time on Amazon EC2 for an exhaustive exploration of all 100 cost tables.Unfortunately right now I can't tell if changing the cost table is affecting the router because it's changing the placement of that last 5% (which has a "ripple effect" on congestion in the LOC'd areas) or whether changing the cost table actually results in significantly different router behavior.In the latter case it's probably worth it for me to try all 100 tables. PS: the device is Spartan-6, which does placement in the map stage, so that's where I'm adding the cost-table flag.I assume the cost table choice gets stashed somewhere in the ncd so that the router can retrieve it... PPS: this is an insanely dense design; it won't even route at 10mhz without the placement constraints.So it might be that I'm operating outside the intended usage model for the par tools.
2018-10-11 14:42
嗨，我想在我的VHDL代码中使用fsm_style属性来在SpartanXC3S200AN设备中的BRAM中实现我的状态机。我在综合后得到的代码和警告如下：HDL代码arcihtecture bla bla ... -statestype状态是（STATE1，STATE2，STATE3，STATE4，STATE5，STATE6，STATE7）;信号状态：states：= STATE1;属性fsm_style：string;属性fsm_style：信号是“bram”;-----------------------------合成报告中的警告警告：Xst：1808- 无法在BRAM中安装FSM（此设备中没有足够的BRAM）。分析FSM以获得最佳编码。使用单热编码优化FSM信号.----------- ------------国家|编码----------------------- STATE1 | 0000001STATE2 | 0000010STATE3 | 0000100STATE4 | 0010000STATE5 | 0001000STATE6 | 0100000STATE7 |百万-----------------------当设备内部有7个状态的16个BRAM时，合成器如何表示（此设备中没有足够的BRAM）？提前致谢，bbinb以上来自于谷歌翻译以下为原文Hi, I wanted to use fsm_style attribute in my VHDL code to implement my state machine in BRAM in a Spartan XC3S200AN device. The code and warning I got after synthesis is below: HDL CODE arcihtecture bla bla ... -- statestype states is (STATE1, STATE2, STATE3, STATE4, STATE5, STATE6, STATE7);signal state : states := STATE1; attribute fsm_style : string;attribute fsm_style of state : signal is "bram";----------------------------- WARNING in SYNTHESIS REPORT WARNING:Xst:1808 - Unable to fit FSMin BRAM (there are not enough BRAM in this device).Analyzing FSMfor best encoding.Optimizing FSMon signalwith one-hot encoding.----------------------- State | Encoding-----------------------STATE1 | 0000001STATE2 | 0000010STATE3 | 0000100STATE4 | 0010000STATE5 | 0001000STATE6 | 0100000STATE7 | 1000000----------------------- How can synthesizer says (there are not enough BRAM in this device) when the device has 16 BRAMs inside for 7 states ? Thanks in advance, bbinb
2019-04-01 12:36
我是fpga设计的新手，所以我不知道一段复杂的代码可以存在多长时间，或者是否存在任何此类限制。我正在尝试在Spartan 6 XC6SLX9-3TQG144I设备中合成一个verilog代码，其中包含一个包含120000个案例值的case语句，并且代码中的总行数接近900000.我使用的是ISE 13.2。合成-XST在某些HDL精化步骤中长时间停留（> 8小时至今）。我在具有48 GB RAM的Intel Xeon 8核处理器系统上运行它。令人惊讶的是，它没有使用完整的CPU /内存资源，只使用了大约25％。到目前为止它没有显示任何错误。我怎么知道这个过程是在某个循环中停滞还是在我应该等待的时间？实际上在我的应用程序中，我只是简单地读取17位并行输入，并根据输入的状态向其他设备提供一些输出，因此超出最大值。 2 ^ 17种组合我在长整数变量中编码了120000，就像查找表一样。在运行这个大代码之前，我已经使用5位并行输入测试了相同的代码，即ISIM和Spartan 3E设备上的32个案例值都运行良好。这个应用程序是可行的还是我做错了什么？请帮忙。以上来自于谷歌翻译以下为原文I am new to fpga design so I have little idea how long a complex piece of code can be or is there any such limits. I am trying to synthesize a verilog code in Spartan 6 XC6SLX9-3TQG144I device that contains a case statement with 120000 case values, and total number of lines in the code is close to 900000. I am using ISE 13.2. The synthesize-XST is getting stuck at some HDL elaboration step for a long time (>8 hrs. till now). I am running it on a Intel Xeon 8-core processor system with 48 GB RAM. Surprisingly it is not using the full CPU/Memory resources and using only about 25%. It has shown no errors till now. How do I know whether the process has got stuck in some loop or upto what time I should wait? Actually in my application I am simply reading 17-bit parallel input and giving some outputs to other devices based on the state of the inputs , so out of max. 2^17 combinations I have coded 120000 in that long case variable like a look-up table. Before running this big code I have tested the same code with 5-bit parallel input i.e 32 case values in both ISIM and on a Spartan 3E device which was working fine. Is this application possible or am I doing anything wrong? Please help.
2019-07-18 06:50
