，但是输出内容乱码或表格格式出错； 5、使用自制模板输出，提示Filed to open Excel template（在同事的电脑上，同一模板可正常输出）；目前已采取的解决方法均无效： 1、重装
2017-12-19 14:58
大家好我做SIM 99仿真的时候出现错误 No net associated with %2 in NETLIST filed请高手指点一下原因是什么
2011-05-16 16:59
/ StedyStateOutput / f-1 / FarZone_steady_3D_Far_Filed
2019-01-29 14:21
本帖最后由 一只耳朵怪 于 2018-5-31 14:50 编辑 VPBE以YCC16的格式输出640X480的图像，数据源大小为640x480x2Bytes，无论是filed mode 或是
2018-05-31 07:56
： Error: failed to download Segment[1]Error: failed to download the Filed:/PersonalData/Prj/STM32Prj
2024-03-13 08:34
请教前辈们，ADV7180的datasheet上说过，HS,VS,FILED可配置为timing generator，可以给其它视频提供时序，可测试发现，这些时序在ADV7180没有接入视频信号
2018-11-26 10:00
with all bit filed* set to zero except message counter and the correct CRC to the very first* MCU
2023-03-16 07:10
在Kintex-7 xc7k480tffg901 2013.4我得到：I / O 179/366GT 10/35将设计移植到2014.2后，这变为：I / O 172/366GT 8/35经过一番检查后，似乎GT_COMMON计入2013年4，但不再是2014年.2这解释了GT计数的增量。我还没有弄清楚I / O的不同之处。有没有人注意到并想出来了？以上来自于谷歌翻译以下为原文On a Kintex-7 xc7k480tffg901 In 2013.4 I got: I/O 179/366GT 10/35 After porting the design to 2014.2 this changed to: I/O 172/366GT 8/35 After some inspection it seems that GT_COMMON was counted in 2013.4 but no longer in 2014.2 That explains the delta in GT count. I have not yet figured out what is different for I/O. Has anyone else noticed and figured it out?
2018-10-19 14:22
你好，我最近将Virtex 6设计转换为使用Kintex 7（7K325）在KC705评估板上运行。我也在同一时间从ISE切换到Vivado 2012.4.1进行试用。它看起来很有希望，但仍有一些错误。其中之一是bitgen似乎没有在比特流中插入正确的TIMESTAMP值。我今天在2013年2月8日（我的计算机日期）实现了设计，并且bitgen日志显示：用“409ac175”覆盖“TIMESTAMP”选项USR_ACCESS。在二进制文件中，时间戳为：0100 0000 1001 1010 1100 0001 0111 0101根据XAPP497,32位时间戳格式是dddd dMMM Myyy yyyh hhhh mmmm mmss ssss解码时间戳（yyyy-MM-dd hh：mm：ss）是：2013-01-08 12:05:53一切都是正确的，除了月份应该是02（2月），而不是01。有人可以证实这种行为吗？我确认USR_ACCESSE2块确实读取了bitgen提供的值。顺便说一下，我通过在约束文件中添加以下内容来启用TMESTAMP插入：set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]谢谢，JF以上来自于谷歌翻译以下为原文Hello,I recently converted a Virtex 6 design to operate on the KC705 evaluation board with a Kintex 7 (7K325). I also switched from ISE to Vivado 2012.4.1 by the same occasion to try it out.It looks promising but there are still a few bugs. One of those is that bitgen does not seem to insert the correct TIMESTAMP value in the bitstream. I implemented the design today on Feb 8th 2013 (my computer date), and the bitgen log shows:Overwriting "TIMESTAMP" with "409ac175" for option USR_ACCESS. In binary, the timestamp is:0100 0000 1001 1010 1100 0001 0111 0101As per XAPP497, the 32-bit timestamp format isdddd dMMM Myyy yyyh hhhh mmmm mmss ssssThe decoded timestamp (yyyy-MM-dd hh:mm:ss) is :2013-01-08 12:05:53Everything is right except the month which should be02 (february), not 01.Anyone can confirm this behavior?I confirmed that the USR_ACCESSE2 block indeed read the value provided by bitgen.By the way, I enabled TMESTAMP insertion by adding the following in my constraint file:set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]Thanks,JF
2018-10-23 10:12
在CY8C24X23 A数据页的第24页，表21说明模拟输出缓冲器的输出电阻为1瓦，典型的。我不认为我以前见过这种形式的输出阻抗，我似乎找不到任何在我平常的地方的信息。有人能帮我理解这个吗？提前感谢！ 以上来自于百度翻译 以下为原文 On page 24 of the CY8C24x23A data sheet, table 21 specs the analog output buffer 's output resistance as 1 Watt, typical. I don't think I've ever seen this form of specing output impedance before, and I can't seem to find anything in any of my usual places for information. Could someone help me understand this please? Thanks in advance!
2019-02-27 11:15
