拥有的内容结构与DSP宽度，LUT的宽度，时钟分配资源相同等等...因此，尽管所有这些不同系列（Zynq的处理核心除外）的唯一区别是它们的最小/最大可用尺寸以及Easypath产品的选项。但是我在许多
2019-02-27 13:35
首先，我是一个很长时间的微控制器人，从来没有想过我会得到与hdl一样多的东西。我的帽子是关于Xilinx和工具的。但我还在学习很多东西。我现在只用简单的SPI就遇到了问题。在下面的代码中，当我强制从计算机程序写入时，我可以看到DataToWrite的值在我的逻辑分析器上没有变化。大多数时候输出是正确的。但偶尔我会在SPIData流中看到一个应该是'1'的位而不是零。行为仿真按预期工作，速度很慢（12 MHz SPI时钟）有一些线索我不明白，但也许其他人有1）我在使用ISE 11.1时发现了这个问题。使用它时，写入FFFF会显示一些低位，意外地忽略零。它们在时间上正确对齐。只是我期待在那里看到'1'并且看到零。3）今晚我转到11.4（希望可能解决问题）后，点击为零的位的位置移动到更高位的单个位。4）如果我将DataToWrite [0]信号路由到外部世界，问题就会消失。5）使用DataToWrite将工具的输出与外部差异而不是向外部传播并没有发现任何差异。当信号没有被发送到外部引脚时，我有点希望看到一些东西得到优化，但没有运气。关于下一步该尝试的任何想法？该PCB具有5位易于访问的IO，并且没有jtag，因此无法进行32个调试通道。下一个董事会将有更多。系统时钟为48 MHz.SPI时钟以12 MHz运行。 ClkDiv4实际上以24 MHz运行。 ClkDiv4由48 MHz时钟驱动的计数器导出。状态[0]由48 MHz时钟设置/清除。这是开始写作的指示。//状态机抽出数据通道@（posedge ClkDiv4）开始大小写（状态）IDLE：如果（Status [0]）开始//如果设置，我们需要开始在DataToWrite中传输数据TXBuf SPIClkReg谢谢你的任何建议。以上来自于谷歌翻译以下为原文First, I'm a long time microcontroller guy, and never thought I'd get as far as I have with hdl. My hat is off to Xilinx and the tools. But I'm still learning a lot. I'm stuck on a problem right now with a simple SPI. In the code below, I can see the value of DataToWrite is not changing on my logic analyzer when I force writes from a computer program. And most of the time the output is correct. But occasionally I'll see a bit that is supposed to be a '1' in the SPIData stream instead be a zero. Behavioral simulation works as expected, and speeds are slow (12 MHz SPI clock) There are a few clues that I don't understand, but perhaps someone else does 1) I discovered the problem when I was using ISE 11.1. When using that, writing FFFF would show some low order bits flicking to zero unexpectedly. They are correctly aligned time wise. It's just I was expecting to see a '1' there and a zero was seen instead. 3) After I moved to 11.4 tonight (hoping that might fix the problem), the location of the bits flicking to zero moved to a single bit in the higher orders. 4) If I route the DataToWrite[0] signal to the outside world, the problem goes away. 5) Diff'ing the output of the tools with DataToWrite going to the outside and not going to the outside didn't reveal any difference. I was kind of hoping to see something get optimized away when the signal wasn't getting routed to an outside pin, but no luck. Any thoughts on what to try next? This PCB has 5 bits of easily accessed IO, and no jtag, so 32 channels of debug isn't possible. Next board will have more. The system clock is 48 MHz. The SPI clock is running at 12 MHz.ClkDiv4 is actually running at 24 MHz.ClkDiv4 is derived by a counter driven by 48 MHz clock. Status[0] is set/cleared by the 48 MHz clock. This is the indication to start writing. // State machine to pump out dataalways @(posedge ClkDiv4)begincase (State)IDLE:beginif (Status[0])begin// If set, we need to begin transmission of the data in DataToWriteTXBuf
2019-01-15 10:31
Xilinx 7系列FPGA简介--选型参考
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本文针对使用FPGA进行验证测试所遇到的一些问题提出了相应的解决方法。
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标准单元的ASIC为什么仍是唯一的技术选择？
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随着TD-SCDMA进入大规模商业实验，WiMAX加入ITU成为第4个3G标准，爱立信率先完成LTE全链路高速传输试验，IMT-Advanced 开始提案征集，移动通信越来越多地呈现了多标准共存的局面。
2019-11-07 08:24
