嗨， 我正在为我的设计添加一个NAND闪存。闪存芯片支持源同步接口，可提供高达166MB / s的带宽。但是当我从闪存中读取DDR数据时。 DQS信号从闪存芯片传输到我的FPGA器件，以及与DQS（83M）边沿对齐的数据。为了将不断变化的数据锁存到FPGA中，我需要偏移dqs信号，使其与数据中心对齐。 问题是如何将dqs信号延迟3ns。由于Virtex-6器件中的IODELAYE1资源为31抽头类型，因此参考clk为200M，因此最大延迟时间约为2.5ns（31 * 78ps）。对？ 我该怎么做才能产生3 ns的dq延迟？以上来自于谷歌翻译以下为原文Hi,I am adding a NAND flash to my design. The flash chip supports source synchronous interface which provides up to 166MB/s bandwidth.But whenI read the DDR data from flash. The DQS signal is transfer from flash chip to my FPGA device,along with the data, edge-aligned to the DQS(83M). In order to latch the ever-changing data into FPGA, I need to offset the dqs signal to make itcenter-aligned to the data.The question is that how to delay the dqs signal for 3ns. As the IODELAYE1 resource in Virtex-6 device is 31-tap type, the reference clk is 200M, so the maximum delay time is about 2.5ns(31*78ps). right?What should I do to generate 3 ns delay of dqs?
2019-03-29 14:03
