= 9GHz -->the output is dominated by a 7.18GHzcomponent I have no idea which the problem could
2019-03-18 14:33
嗨，我正在尝试使用OSA上的外部触发功能测量30 mS脉冲。在我开始30mS激光脉冲之前，我似乎需要在触发OSA后给出30 mS的延迟。这听起来是对的还是我错过了什么？谢谢，贾斯汀 以上来自于谷歌翻译 以下为原文Hi, I am trying to measure a 30 mS pulse using the external triggering capability on the OSA.It seems like I need to give a 30 mS delay after triggering the OSA before I start my 30mS Laser pulse.Does this sound right or am I just missing something? Thanks, Justin
2018-10-19 11:38
我在Spartan3e汽车fpga的1.2v引脚上看到1v，可能更低，为1.4变化。我也无法正确初始化jtag链，Impact看到链中有上述fpga的17个未知设备。如果上面的fpga不在jtag链中，影响请参见其他jtag芯片。所以我想知道12.v供应是否是问题？以上来自于谷歌翻译以下为原文I'm seeing a 1v, maybe a lttle less, to 1.4variation on the 1.2v pins of a Spartan3e automotive fpga. I also can't initialize the jtag chain correctly, Impact sees 17 unknown devices with the above fpga in the chain.Impact see the other jtag chips correclty if the above fpga is not in the jtag chain. So I'm wondering if the 12.v supply is the problem ?
2019-06-24 08:08
有人能告诉我，如果一个校准负载固定负载在3 GHz以下的52 dB URL是如何验证的，那不是在DC而不使用另一个校准套件/网络分析仪系统？ 以上来自于谷歌翻译 以下为原文Can someone tell me how is a cal kit fixed load verified bellow 3 GHzfor it’s 52dBRL , that is other than at DC and without using just another cal kit/ network analyzer system?
2019-07-09 09:20
嗨，AllI有一个非常困难的问题：（经过几天的正常工作，DSPIC30F5011卡在一个未知的状态。只有重置可以释放它。两个提示：1。SW实现16秒看门狗，在这个问题STATE2中似乎没有激活。SW实现休眠模式3。我确信睡觉后，看门狗被启用（制作测试）4。当CPU被卡住时，我可以通过示波器看到XTAL振荡器是活动的-我断定它目前不在睡眠模式5。通过MCLR引脚使CPU复位，使其返回到DIFSP30F5011到LIFL6就足够了。我运行所有的“永远循环”，我没有发现任何可能导致这个问题，特别是因为看门狗假定是Actuvi7。我正在使用两个CAN总线。所有陷阱只实现ASM（“重置”），除了实现“InSCONTROBER失败”，实现ItCON1BITS OSCWORKS＝0；γ-DelayyMS（900）；ASM（“RESET”）；9。在我测试的一个单元中，CPU似乎在唤醒后重置自己。奇怪。我现在正在检查勘误表。没有发现任何特殊的，但仍在检查…谢谢大家，即使是阅读到目前为止：最好的 以上来自于百度翻译 以下为原文 Hi All I have a very hard problem :( After couple of days working correctly, the dspic30f5011 gets stuck in an unknown state. Only Reset can free it. couple of hints:1. The SW implements 16 seconds Watchdog which does not seems to be activated in this issue state2. The SW implements sleep mode3. I made sure that after sleep, watchdog is enabled (made test)4. While CPU is stuck, i can see via osciloscope the XTAL oscillator is active - i concluded it is NOT currently in sleep mode5. It is enough to make a CPU Reset via MCLR pin to return it the dspic30f5011 to life6. I run over all "forever while loops" and i didn't find anything that can cause the issue, especially since Watchdog assumes to be active7. I am using two of the CANbus8. All traps implements only asm("RESET") besides "_OscillatorFail" which implements INTCON1bits.OSCFAIL = 0; __delay_ms(900); asm("RESET");9. In one unit i tested, it seems the CPU resets itself after wakeup. Strange.10. I am now checking the Errata. Didn't find anything special yet but still checking... Thank you all, even for reading so far :) Best RegardsRan
2019-05-07 12:26
SOLT校准后，我将短负载连接到一个端口。阻抗点不在S11史密斯圆图的短路点上，而是旋转一定程度。开放负载也是如此。但它们的相位差是180度。为什么？ 以上来自于谷歌翻译 以下为原文After SOLT calibration, I connect the short load to one port. The impedance point is not on the short circuit point of the S11 Smith Chart, but rotates by some degrees. So does the open load. But their phase difference is 180 deg. Why?
2018-12-28 15:52
嗨，我正在使用Spartan 6 FPGA，xc6slx25-3ftg256。微控制器的一个OUput总线缓冲器看起来像这样OBUF_inst_ad_o_0：OBUFgeneric map（DRIVE => 12，IOSTANDARD =>“DEFAULT”，SLEW =>“SLOW”）端口映射（O => ad_o（0）， - 缓冲区输出I => ad_o_s（0） - 缓冲区输入（直接连接到顶级端口））;放在Bank2和LVCMOS33中。在PlanAhead中，片外终端设置为FP_VTT_50。我将其更改为NONE并保存。当我再次打开片外终止时再次是FP_VTT_50。所以我想知道是因为Drive Strength 12mA？如果我改为8mA，则它变为NONE。如果我必须使用FP_VTT_50类型的终端，那么在电路板上占用大量的位置来为16位总线放置所有50欧姆。如果我改变任何属性，大多数输出都有*。这是什么意思？任何人都可以告诉我什么是推荐的？片外终端取决于频率？如果是，频率是多少？非常感谢提前。问候，基兰以上来自于谷歌翻译以下为原文Hi,I m using Spartan 6 FPGA, xc6slx25-3ftg256. One Ouput bus buffer to Microcontroller looks like this OBUF_inst_ad_o_0 : OBUFgeneric map (DRIVE => 12,IOSTANDARD => "DEFAULT",SLEW => "SLOW")port map (O => ad_o(0),-- Buffer outputI => ad_o_s(0) -- Buffer input (connect directly to top-level port)); Placed in Bank2 and LVCMOS33. In PlanAhead Off-Chip Termination is set to FP_VTT_50. I change it to NONE and saved it. When i open again Off-Chip Termination is again FP_VTT_50. So i m wondering is it because of Drive Strength 12mA?If i change to 8mA then it changes to NONE. if i have to use FP_VTT_50 kind of termination then it takes lot of place on the board to place all the 50 Ohm for a 16-bit bus. Most of the outputs is having * if i change any attributes. What does it mean?Can anyone please tell me what is recommended? Off-Chip termination depends on frequency? if yes what is the frequency? thanks a lot in advance. Regards,Kiran
2019-06-14 13:07
模拟设计的100条圣经
2021-02-25 07:24
[解决方案] 2011/2018：问题不存在如所描述的那样。DMA传输未暂停。由于逻辑分析仪的错误触发器，我看了一个错误的数据传输。]用逻辑分析仪查看我的PIC的两个不同SPI外设的信号，我惊讶地看到，我的DMA SPI传输（写入512个字节到闪存）被CN（IOC）中断/暂停。中断服务例程，它访问另一个SPI外围设备。只需注意：传输和中断工作得很好，这只是我想优化的时机。在我看来，DMA传输的想法是在没有MPU的情况下工作（使用SPI重复的连续模式），所以我没有想到MPU中断对DMA传输有影响。它。我的意图是，DMA传输应该继续而不是等待另一个（无关的）中断。虽然我有一个模糊的理解，DMA SPI传输确实依赖于内部的中断逻辑，但我还没有找到文档中的细节的解释，尤其是我如何才能解释。观察到的行为。我必须注意中断优先级还是应该继续搜索哪个方向…这里是一些背景信息。前4个频道显示了512字节DMA SPI传输（SPI 2）的摘录，它被CN中断（底部4通道）打断。CN中断例程读取来自另一SPI外围设备（SPI 1）的数据的七个16位字，即在最后4个通道中看到的数据传输也反映中断的长度。在中断退出时，DMA继续工作。在ButtoMod中看到的图像是中断功能。这是对DMA SPI传输的SPI 2的一次初始化，这是一个函数，它实际上对512字节的附加信息进行DMA传输：嵌套中断被启用（而不是DI）。中断优先级是所有4（这是复位后的默认值，例如，πSPI2TXIP，πSPI2IP）（设置为3，对于SPI2不改变行为）在这个PIC的中断向量表中。CN中断位于γ-SPI2中断和γ-SPI2TX中断之前，即“自然优先级”F。或CN高于SPI2（第8.1章FRM） 以上来自于百度翻译 以下为原文 ["solution" 11.Jan.2018:the problem does not exist as described. The DMA transfer is NOT paused. Due to wrong trigger for the Logic Analyzer, I looked at a wrong data transfer.]Looking at the signals of two different SPI peripherals of my PIC with a logic analyzer, I was a bit astonished to see that my DMA SPI transfer (writing 512 bytes into a flash memory) is interrupted/paused by a CN (IOC) interrupt service routine, which accesses another SPI peripheral.Just to note: the transfers and interrupts work perfectly,- it's just the timing which I would like to optimize.In my mind the idea of a DMA transfer is to work without the MPU (using SPI repeated continous mode), so I did not expect an MPU interrupt to have influence on the DMA transfer, by delaying it. My intention is that the DMA transfer should continue and not wait for another (unrelated) interrupt.While I have a vague understanding that the DMA SPI transfer DOES depend on interrupt logic internally, I did not yet find an explanation of the details in the documentation, especially how can I change the observed behaviour.Do I have to pay attention to interrupt priorities or in which direction should I continue to search ... Here is some background information The top 4 channels shows an excerpt of the 512 byte DMA SPI transfer (SPI 2), which is interrupted by a CN interrupt (bottom 4 channels). The CN interrupt routine reads seven 16-bit words of data from another SPI peripheral(SPI 1), i.e. the data transfer seen in the last 4 channels also reflects the length of the interrupt. On exit of interrupt, the DMA continues to work. See image at bottom This is the interrupt functionvoid __attribute__((interrupt, auto_psv)) _CNInterrupt(void){if (_IOCFB10) { spiReadData16(ICM_ACCEL_XOUT_H, (WORD *) dataICM.iData, ICM_DATA_COUNT); bIcmDataReady = 1; _IOCFB10 = 0;} _CNIF = 0;// clear interrupt flag}This is some one-time initialization of SPI #2 for the DMA SPI transferSPI2CON1bits.MODE16 = 0; // byte modeSPI2CON1bits.MSTEN = 1;//SPI Master SPI2CON1bits.CKP = 0; // Idle state for clock is a low levelSPI2CON1bits.CKE = 1;SPI2CON1bits.ENHBUF = 0;SPI2STATLbits.SPIROV = 0; // clear the Receive overflow flagSPI2BRGLbits.BRG = 0;SPI2CON1bits.MCLKEN = 0;// SPIEN enabled; DISSDO disabled; MCLKEN FOSC/2; CKP Idle:Low, Active:High;//SSEN disabled;MSTEN Master; MODE16 disabled; SMP Middle; DISSCK disabled;// SPIFE Frame Sync pulse precedes;CKE Idle to Active; MODE32 disabled;// SPISIDL disabled; ENHBUF enabled; DISSDI disabled;SPI2CON1Hbits.IGNROV = 1;SPI2CON1Lbits.SPIEN = 1;// enable SPI2 peripheraland this is the function which actually does DMA transfers of 512 bytesstatic void dmaWrite(BYTE *pBuf, WORD wCount, WORD wMode){ DMACON = 0x0001; // DMACONbits.DMAEN = 0; DMAH= DMA_UPPER_LIMIT; DMAL= 0x0000; // CHEN enabled; DAMODE Unchanged; TRMODE One-Shot; CHREQ disabled; // RELOAD disabled; SIZE 8 bit; NULLW disabled; SAMODE Incremented; // HALFIF disabled; LOWIF disabled; HALFEN disabled; DONEIF disabled; // OVRUNIF disabled; CHSEL SPI2 Event; HIGHIF disabled; DMACH0 = 0; // SPI"repeated continous mode" DMACH0bits.TRMODE=0;// Transfer mode DMACH0bits.SAMODE=1;// Source address increment mode DMACH0bits.DAMODE=0;// dest DMACH0bits.SIZE=1;// byte DMACH0bits.NULLW=0;// null write disable DMAINT0= 0x00; IFS0bits.DMA0IF = false; _DMA0IE = 1;// enable interrupt // for CHSEL see FRM Table 5-1 DMAINT0bits.CHSEL = DMA_TRIG_SRC_SPI2_TRANSMIT; //Trig on SPI2 TX DMASRC0= (WORD) pBuf; DMADST0= (unsigned int)&SPI2BUFL; DMACNT0= wCount; _SPI2TXIF = 0; SPI2IMSKLbits.SPITBEN = 1;// interrupt if tx empty // Clearing Channel 0 Interrupt Flag; IFS0bits.DMA0IF = 0; //Enable DMA DMACONbits.DMAEN = 1; //Enable DMA Channel 0 DMACH0bits.CHEN = 1; DMACH0bits.CHREQ = 1; // note, actually the end of the DMA transfer is signalled end handled // by a DMA interrupt, not shown here}Additional information:Nested interrupts are enabled(not disabled)Interrupt priorities are all 4 (which is the default after reset, e.g. _SPI2TXIP, _SPI2IP)(setting them to 3 for SPI2 does not change the behaviour)In the interrupt vectors table for this PIC the CNInterrupt comes BEFORE the __SPI2Interrupt and __SPI2TXInterrupt,i.e. the 'natural priority' for CN is higher than for SPI2 (chapter 8.1 FRM) Attached Image(s)
2018-11-22 15:14
首先，祝大家圣诞快乐。我花了一些圣诞节来讨论我的8720D VNA - 它是由我个人拥有的，因此在我的家里，所以它不像它看起来那么不干净！我感兴趣的是看一个未连接的公N连接器是否可以用作“开放式”校准设备，如果是，那么哪个参数最好。好吧，我知道它可以完成，因为FieldFox系列上的QuickCal可以做到这一点，但当然我需要参数进入VNA。如果他们是安捷伦的老手，我也不会感到惊讶。首先使用适当的'N'校准套件（85032B）进行校准后，我注意到以下情况。 1）令我惊讶的是，开放式N似乎不是电容性的，因为我认为由于边缘电容。相反，它似乎是归纳的。是否能够通过值为2的电容器来表示电感。中心导体位于参考平面下方约1 mm。鉴于真空中的光速为299792458 m / s，这表明输入的偏移应为-0.001 / 299792458 = -3.335 ps。那有意义吗？也许值得说明偏移几ps - 使其更负面，因此可以将电容作为正值输入。我不确定这是否比使用负电容更好或更差。对于它的价值，我最初尝试通过曲线拟合找到C0，C1，C2和C3的合理值并不太成功，但我怀疑它有更多的时间可能是可行的。如果有人试过这个，或者知道参考文献，我会感兴趣的。你可能觉得我很生气，但现在是圣诞节，所以我喝了一两杯啤酒！有了这一切，一切顺利。我要去爱尔兰咖啡吧！ （这在英国很受欢迎 - 对美国不太确定。我猜你可以用杰克丹尼尔威士忌制作它。）如果我说实话，我用一种廉价的苏格兰威士忌制作“爱尔兰咖啡”。我认为将更昂贵的爱尔兰威士忌放入咖啡中是不合理的。戴夫 以上来自于谷歌翻译 以下为原文First of all, merry Christmas to everyone. I've spent some of Christmas day messing around with my 8720D VNA - it is personally owned by me, hence in my home, so it was not quite as unsociable as it might appear! I was interested in see if an unconnected male N connector could be used as an "open" calibration device, and if so what parameters would be best. Well, I know it can be done, as the QuickCal on the FieldFox range do this, but of course I needed the parameters to enter into the VNA. and I would not be surprised if they are proprietry to Agilent. I noticed the following, after first calibrating with a proper 'N' calibration kit (85032B). 1) Much to my surprise, the open-N does not appear to be capacitive, as I would have thought due to the fringing capacitance. Instead, it appears inductive. Would it make sence to represent an inductance by capacitor of a value < 0 ? I found it is possible to enter negative values for all value C0, C1, C2 and C3. . 2) The centre conductor sits below the reference plane by about 1 mm. Given the velocity of light in a vacuum is 299792458 m/s, that would suggest the offset to be entered should be -0.001/299792458 = -3.335 ps. Does that make sense? Perhaps it is worth lying about the offset by a few ps - making it even more negative so it is possible to enter the capacitance as a positive value. I'm not sure if that would be better or worst than having negative capacitors. For what it is worth, my initial attempts to find sensible values for C0, C1, C2 and C3 by curve fitting were not too successful, but I suspect with more time it might be workabe. If anyone has ever tried this, or knows of a reference, I'd be interested. You probably think I am mad, but it is Christmas day, so I have had a beer or two! With that, all the best. I'm going to have an Irish Coffee! (That's quite popular in the UK - not so sure about the USA. I guess you could make it with Jack Daniels whisky.) If I'm honest, I make an "Irish Coffee" using a cheapish Scotish whisky. I think putting the more expensive Irish whisky in a coffee is not justified. Dave
2019-04-28 11:34
