the files into ISE, I found it lacks some files.I searched all the directories, but still can't find them. Thanks for your help in advance.Cook
2019-02-21 11:31
to 40GHz).I am looking for a sort of cook book method (step by step) if you will, on how to do
2019-02-15 06:01
大家好。我正在编写PIC18F4685，但在与PICTIT2进行连接的那一刻，显示了“没有检测到设备”的信息。我已经测试了3个不同的图片相同的参考，问题仍然存在。我也做了故障排除测试，一切都井然有序。我的示意图如下：I也改变了电容器，最大到10uF，没有任何成功。 以上来自于百度翻译 以下为原文 Hi everyone. I am programming a PIC18F4685, but at the moment of making the connection with the pickit2 this shows the message: "No Device Detected". I have tested with 3 different PICs of the same reference and the problem persists. I also did the Troubleshoot Test and everything is in order. My schematic is as follows: http://i65.tinypic.com/30c0k2c.jpg I have also changed the capacitors up to a maximum of 10uf without getting any success.
2019-03-22 09:01
如何才能成为一个数字验证工程师？
2021-09-18 09:17
大家好，我是Vittorio，我是fpga和vhdl的初学者，我正在使用spartan3-e demoboard和digilent的Lcd。我有这个问题，也许一些专家可以帮助我理解。请参阅下面的代码如果输入引脚上的转换发生变化，我想驱动四个LED。如果输入引脚为“1”，则如果输入引脚为“0”，则希望相继打开芯片1毫秒，并依次关闭所有LED。我的问题是LED同时开启和关闭......这是什么交易？先谢谢你。图书馆IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_ARITH.ALL;使用IEEE.STD_LOGIC_UNSIGNED.ALL;----如果实例化，则取消注释以下库声明----本代码中的任何Xilinx原语。 - 图书馆UNISIM; - 使用UNISIM.VComponents.all;实体Powersequencer是 端口（VDDCHK：STD_LOGIC; CLK：在STD_LOGIC中; VDD：输入STD_LOGIC; VDDIN：输入STD_LOGIC; VH：inout STD_LOGIC; COMn：inout STD_LOGIC）;结束权力顺序;建筑行为的力量序列是开始过程（CLK，VDDCHK）开始如果VDDCHK ='1'那么VDD VDDIN VH COMn elsif VDDCHK ='0'然后VDD VDDIN VH COMn结束if;结束过程;结束行为;以上来自于谷歌翻译以下为原文Hello All, i'm Vittorio and i'm a beginner in fpga and vhdl, i'm using spartan3-e demoboard with Lcd from digilent. i have this issue and maybe some expert can help me to understand. pls see the code below i would like to drive four LED if a contition on the input pin change. If the input pin is "1" a would like turn on chip in sequence by 1millisecond from eachother and turn off all led in sequence if the input pin is "0". my problem is the LED turns on and off simultanusly... what's the deal? thank you in advance. library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all; entity Powersequencer is Port ( VDDCHK : inSTD_LOGIC;CLK : inSTD_LOGIC;VDD : inoutSTD_LOGIC;VDDIN : inoutSTD_LOGIC;VH : inoutSTD_LOGIC;COMn : inoutSTD_LOGIC);end Powersequencer; architecture Behavioral of Powersequencer is begin process (CLK, VDDCHK) beginif VDDCHK='1' then VDD
2019-05-13 13:04
want to cook any more PIC24 devices until I can find out what or if I am doing something wrong so
2019-07-17 13:10
什么是GNU Radio？ 开放的软件无线电平台有什么优势？
2019-08-02 08:13
