%------------------------------------------------------------------function converged = batchUpdate% Every
2015-07-23 17:34
我们在集群中添加了一个新节点，我们在服务器中安装了2个Intel X710-T4卡。我们的两个SAN目前只有1Gb（我们有Tegile T3100和联想px12-450r）。每当我尝试使用这些NIC上的其中一个端口设置SAN连接时，都会导致各种问题。我们有CSV离线并且报告已损坏且无法读取，我们丢失了VM配置，并且VM停止从此节点（2016 Hyper V群集）托管的任何卷启动。奇怪的是，在我们更新/迁移到2016之前，这个节点在我们的2012集群中工作正常。我有适配器的最新驱动程序。以下是发生的一些事情： - 当我最初将节点带入集群时，我使用X710-T4配置了所有3个与SAN的连接（2个用于每个独立交换机/控制器的tegile，1个用于直接连接的lenovo）。每当此节点获得Lenovo上任一卷的所有权时，该卷上的VM将不再启动。他们会给出不同的奇怪启动错误，最终它甚至会硬锁定联想SAN本身，我必须硬启动它。我将该连接移至板载broadcom 1Gb NIC并解决了这些问题。 tegile仍然通过X710-T4连接，当它继续运行时，这里也发生了一些奇怪的事情。有时，连接的iSCSI设备列表在该节点上只是空白，即使它仍在运行。在最新的情况下，节点从Tegile获得LUN的所有权，并且该LUN上的所有VM立即停止工作，并且CSV报告为损坏且不可读。我将CSV移动到另一个节点，过了一会儿它终于再次开始工作了。问题是此节点坚持取得存储节点的所有权，并且似乎没有办法阻止它（无法在CSV上设置节点首选项）。所以现在我害怕取消暂停这个节点，我正在考虑将Tegile连接转移到broadcom中，并希望避免所有的麻烦....但是当我们最终升级我们的SAN并转到10Gb我不想运行再次进入这个问题。我意识到这可能难以破译......在这一点上，我只是在寻找建议。它是适配器属性之一吗？连接到SAN的适配器除了未选中IPv4之外的所有协议，它们将巨型帧设置为9014并且它们被设置为不允许操作系统将其关闭（省电的事情）。除此之外，它们基本上处于默认设置。我想我可能会在这些适配器上禁用SRV-IO，但这是导致我的问题（我对此表示怀疑）。让我知道你的想法！以上来自于谷歌翻译以下为原文We added a new node to our cluster and we've got 2 of the Intel X710-T4 cards in the server. Both of our SANs are currently only 1Gb (we have a Tegile T3100 and a Lenovo px12-450r). Whenever i try to setup SAN connections using one of the ports on these NICs it causes all sorts of issues. We have CSVs go offline and report being corrupted and unreadable, we've lost VM configs and VMs stop booting from any volumes that are being hosted by this node (2016 Hyper V cluster). The odd part is that this same node was working fine in our 2012 cluster before we updated/migrated into 2016. I have the latest drivers for the adapter. Here are some things that have happened: - When I initially brought the node into the cluster I configured all 3 connections to the SANs using the X710-T4 (2 for the tegile for each independent switch/controller and 1 for the lenovo which is directly connected). Right off the bat each time this node took ownership of either volume on the Lenovo the VMs that were on that volume would no longer boot. They would give different weird boot errors and eventually it would even hard lock the Lenovo SAN itself and I'd have to hard boot it. I moved that connection down to the onboard broadcom 1Gb NIC and that solved those issues. The tegile was still connected via the X710-T4 and while it continued to operate, some odd things happened here as well. Sometimes the list of connected iSCSI devices would just be blank on that node even though it was still operating. In the latest case the node took ownership of a LUN from the Tegile and immediately all the VMs on that LUN stopped working and the CSV reported as corrupt and unreadable. I moved the CSV to another node and after a while it finally started working again. Problem is this node insists on taking ownership of storage nodes and there doesnt appear to be a way to stop it (cant set node preferences on CSVs). So right now I'm scared to unpause this node and am contemplating just moving the Tegile connections into the broadcom as well and hopefully avoid all the hassle.... but when we eventually do upgrade our SAN and go 10Gb I dont want to run into this issue again. I realize this is probably incredibly hard to decipher... at this point I'm just looking for suggestions. Is it one of the adapter properties? The adapters that connect to the SANs have all protocols except IPv4 unchecked, they have jumbo frames set to 9014 and they are set to not allow the OS to turn them off (power saving thing). Aside from that they are basically at default settings. I think I could probably disable SRV-IO on these adapters but is that causing my issue (I doubt it). Let me know what you think!
2018-11-15 11:15
您好我正在使用FET_IV_Gm_PowerCalc（设计指南>放大器> DC和偏置点）来设计功率放大器并找到偏置点。但是当我把我的晶体管Spice模型（我从制造商网站获得）而不是默认晶体管时，它不能正常工作并且IV曲线不正确。我的晶体管是Semelab的D2201UK，输出功率为2.5 W.问题是什么？最好的问候。编辑：m_zerang于2015年5月23日下午2:41 Untitled1.png147.2 KB 以上来自于谷歌翻译 以下为原文Hi I am using FET_IV_Gm_PowerCalc (design guide>Amplifier>DC and Bias point) for designing a Power amplifier and finding Bias point. but when I put my transistor Spice model ( I got it from manufacturer site) instead of default transistor, it doesn't work good and the IV curve is incorrect. My transistor is D2201UK from Semelab with 2.5 W output power. what is the problem? Best Regards.Edited by: m_zerang on May 23, 2015 2:41 PM附件Untitled.png149.3 KBUntitled1.png147.2 KB
2018-10-19 11:41
我有一个IPMM，上面装有绝对位置旋转变压器。不幸的是，即使使用解码器也无法使用它 - 绝对位置为12-16位并行接口。这就是为什么我尝试使用2个绝缘电流传感器在无传感器模式下运行。 我尝试使用3.0和MCWB 1.2，但无法运行中断和串行通信。之后我尝试使用3.2和workbench 2.0并正确编译了FW。当尝试将MCWB 2.0连接到FW 3.2时，会出现一些错误，指出某些版本不兼容。我将FW 3.2（带有MCWB2.0生成的参数）与MCWB 1.2的串行通信连接起来。然后我让电机旋转几圈。 它的行为如下：首先它运行DC几毫秒，然后产生9个正弦波，频率为20 Hz，最大电压（PWM 0-100％）。之后电机停止并显示速度反馈错误。 在10或20次运行中的一次运行中，FW暂时停止电机上的DC并且与PC失去通信。我必须重置电路板，这样我才能重新工作。 请告诉我我做错了什么，所以我无法在无传感器模式下运行电机？电机参数非常关键吗？ 还有什么不对，所以FW 3.2无法与MCWB 2.0通信？以上来自于谷歌翻译以下为原文 I have an IPMM with absolute position resolver mounted on it. Unfortunately i can not use it even with decoder - absolute position to 12-16 bit paralel interface. Thats why i try to run in sensorless modes with 2 insulated current sensors. I tried with 3.0 and MCWB 1.2 but wasnt able to run the interrupts and the serial communication. After that i tried with 3.2 and workbench 2.0 and the FW compiled correctly. When try to connect MCWB 2.0 to FW 3.2 there is an error that says some version incompatibilities. I connect FW 3.2 (with parameters generated from MCWB2.0) with serial communication to MCWB 1.2. Then i have the motor spinning just for few turns. It behaves like that: First it runs DC for few miliseconds and after that it generates 9 sine waves with frequency 20 Hz and maximum voltage (PWM 0-100%). After that the motor stops and displays Speed Feedback Error. In one of 10 or 20 runs the FW halts on the moment with the DC on the motor and looses commmunication with the PC. I have to reset the board so i can have it working again. Please tell me what i do wrong so i can not run the motor in sensorless mode? Is it very critical about motor parameters? Also what is wrong so FW 3.2 can not communicate to MCWB 2.0 ?
2019-04-15 11:56
如何实现基于RK3399开发板的cartographer激光SLAM建图模块的设计？
2022-03-07 07:05
第一部工业以太网解决方案的优势和作用目前，世界各地的制造工厂都依赖以太网解决方案来满足工业应用对实时性能和耐用性的要求。与传统现场总线相比，以太网能提供更快的速率，能更好地处理大批量数据，最终还能通过卓越的能效比和更加高效的设备节省更多开支。以太网还能单挑重任，作为唯一的组网技术，把车间的自动化系统连接到用于控制车间的企业IT系统——在提升性能的同时简化网络的整体设计。
2019-07-18 07:40
亲爱的成员们，我正在设计高速ADC / DAC，我想提取相同的PCB模型来进行协同仿真。我的提取流程是导出Allegro布局，在ADS中导入并进行EM仿真，然后使用宽带SPICE模型生成器来获得等效的HSPICE模型。但是有一些问题。试图简化问题我只布置两条50欧姆特性阻抗线（从allegro寄生显示器看），长度为34毫米。在每个前端连接两个50欧姆电阻作为Rsig和Rload，然后我运行一些模拟。这是我的一些问题。问题1.我输入DC 1.0V信号，但DC值超出预期，等效直流电阻似乎大于Allegro的值，PCB的每一侧的电压应该接近。但事实并非如此。问题2 S21处于较高频率（例如：2GHz）是如此之小，从而影响高速模拟结果。问题3对于DAC协同仿真，我输入低频方波（Tr / Tf = 50p或更高）以查看结果。但输出显然是错误的，包括瞬态和稳定时间。更不用说更高频率的结果（例如：2GHz）。我的EM设置为0~20GHz，20pts，这对于那些条件是否足够？我认为这可能是我的一些选项设置错误。我真的很感谢你的帮助。谢谢。 以上来自于谷歌翻译 以下为原文Dear members, I'm designing high speed ADC/DAC, and I want to extract the equivalent model of PCB to do the co-simulation. My extraction flow is that export Allegro layout, import in ADS and do EM simulation, then using Broad Band SPICE Model Generator to have equivalent HSPICE model. But there's some problems. Trying to simplified the problem I only layout two line with 50 ohm characteristic impedance (seen from allegro parasitic display) and the length is 34mm. Connecting two 50 ohm resistor at each front end as Rsig and Rload, then I run some simulations. Here's some of my problems. Problem 1. I input DC 1.0V signal but the DC value is out of expectation, the equivalent DC resistance seems to be larger than the value from Allegro, which the voltages on each side of PCB should be close. But it is not. Problem 2 The S21 is at higher frequency (ex: 2GHz) is so small, consequently affect the simulation result at high speed. Problem 3 For DAC co-simulation, I input low frequency square wave (with Tr/Tf =50p or more) to see the result. But the output is obviously wrong, including the transient and stable time. Not to mention higher frequency result(ex: 2GHz). My EM setup is 0~20GHz with 20pts, is that enough for those condition? I think it may be some of my option setting errors.I really appreciate for your help. Thank you.
2019-02-13 15:16
高性能数据中心的网络演进趋势开源100Gbps NIC（Corundum）架构简介基于流水线的队列管理基于Xilinx Alevo U50和VCU118 板卡的测试
2021-01-28 07:14
所有，我有一个由聚酰亚胺制成的柔性电路（er = 3.3到3.5），我想用ADS2011布局确认单端微带线和差分偶数/奇数模式走线的阻抗。我已将Gerber文件加载到工具中，我可以设置多个端口。我的目标是在存在交叉阴影平面（非实心）的情况下提取单端/差分阻抗。柔性电路在动态环境中使用，并且它不能是实心平面参考，因为它会使其疲劳，并最终随着时间的推移而失效（裂纹迹线等）。我想调整走线和交叉影线参数以达到90欧姆差分阻抗和50欧姆单端。我将在两种情况下分解问题 - 差分和单端。我想为差分设置一个案例，并为偶数和奇数模式提取迹线的阻抗。我相信这在ADS中是小菜一碟，我只是不知道如何设置它。我知道我可以转换阻抗Z11 = 50 *（1 + S（1,1））/（1-S（1,1））。从这里我如何得到奇数和偶数模式？如何对交叉影线进行参数化，以便我可以改变一些参数并查看阻抗变化？我真的很感激任何帮助。我挖了我的旧书，我重新找到偶数= Z11 / 2 odd = 2 * Z11的阻抗。但是，我只需要知道我需要在跟踪上放置多少个端口。对于差分情况，我想这是一个双端口测量，但是地面参考怎么样？我会把以下端口P1，P2分别对一端进行差分对。 P3，P4到另一端，地面怎么样？它只是P5吗？然后我将其导出到原理图，并添加地面，因为我无法在布局中添加地面？任何帮助将不胜感激。这是我通过实验和FCC测试得到的经典案例，但我没有模拟模型来预测这一点而不需要迭代flex。谢谢rjrodrig 以上来自于谷歌翻译 以下为原文All, I have a Flex circuit made out of Polyimide (er =3.3 to 3.5), I want to confirm the impedance of single ended microstrip and differential even/odd mode traces using ADS2011 Layout.I have loaded the Gerber files into the tool, and I can setup multiple ports.My goal is to extract the single ended/diff impedance in the presence of a cross-hatched plane (not solid).The flex circuit is used in a dynamic environment, and it cannot be a solid plane reference as it will fatigue it, and eventually fail over time (cracked traces etc).I want to adjust the traces, and cross-hatch parameters to hit 90 ohms differential impedance, and 50 ohms single ended. I will split the problem in two cases -- the differential and single ended.I want to setup a case for the differential, and extract the impedance of the traces for even and odd mode.I am sure this is a piece of cake in ADS, I just don't know how to set it up.I know I can convert the impedance Z11 = 50*(1+S(1,1))/(1-S(1,1)).From here how do I get odd and even mode?How do I parametrize the cross hatch so I can vary the some parameters and look at the impedance changes? I would really appreciate it any help.I have dug up my old books and I recapped the impedance for even=Z11/2 odd=2*Z11.However, I just need to know how many ports I need to put on my traces. For the differential case, I imagine this is a two port measurement, but what about the ground reference?I would put the following ports P1,P2 to diff pair one end. P3,P4 to the other end, what about ground? Is it just P5?Do I then export this to schematic, and add ground since I can't add ground in Layout? Any help would be greatly appreciated.This is a classical case I have gotten around experimentally and through FCC testing, but I don't have a simulation model to predict this without iterating the flex. Thanks rjrodrig
2019-01-08 15:24
