we change register concatenation data (eg. OUTX_H&OUT_L: FD5Ch) into a 10-bit data (eg. X: -676
2018-09-10 17:18
为SampleSwitchWarning[Pe1665]: concatenation with "=" in macro "HAL_CONFIG_IO_OUTPUT_PREP"
2018-05-22 00:18
for concatenation; which is how I understand the PROMGen tool to work.Is there a way to save flash space and only store a single copy of this bitstream?
2019-06-21 12:05
这是一个我以前从未见过的奇怪表达。 “2”（蓝色）在下面的表达式中是什么意思？input [3：0] frame_sync_offset;wire [5：0] fs_delay = fs_fixed_delay-{{2 {frame_sync_offset [3]}}，frame_sync_offset};以上来自于谷歌翻译以下为原文This is a strange expression I have not seen before. What does the "2" (in blue) mean in the following expression? input [3:0]frame_sync_offset; wire [5:0]fs_delay = fs_fixed_delay - {{2{frame_sync_offset[3]}},frame_sync_offset};
2019-03-28 13:20
对于我的任务，我必须将计数器连接到寄存器文件。显然，这不是完整的代码，我只包括组件：计数器：图书馆IEEE;使用IEEE.std_logic_1164.all;使用IEEE.std_logic_misc.all;使用IEEE.std_logic_arith.all;实体柜台是 通用（延迟：时间：= 8 ns）; 端口（Clk：在std_logic; Inc：在std_logic; Rst：在std_logic; i：out std_logic_vector（2 downto 0）; j：输出std_logic_vector（2 downto 0）; k：输出std_logic_vector（2 downto 0））;结束柜台;计数器的架构行为是 开始 P：流程（Clk） 变量值：UNSIGNED（8 downto 0）：=“000000000”; 开始 if（Clk'event和Clk ='1'）然后 if（Rst ='1'）然后 值：=“000000000”; elsif（Inc ='1'）然后 值：=值+ 1; 万一; 万一; I（2）注册：图书馆ieee;使用ieee.std_logic_1164.ALL;使用ieee.std_logic_unsigned.ALL; 实体RegFile IS 通用（延迟：时间：= 8 ns）; 端口（R_addr1，R_addr2，W_addr：IN std_logic_vector（7 DOWNTO 0）; R_en1，R_en2，W_en：IN std_logic; R_data1，R_data2：OUT INTEGER; W_data：IN INTEGER; Clk：IN std_logic）;结束RegFile;RegFile IS的架构行为 RF类型是INTEGER的数组（0到31,0到7）; 信号存储：RF：=（ ...）; --8 x 8矩阵开始 WriteProcess：Process（Clk） 变量col_w：std_logic_vector（2 DOWNTO 0）; 变量row_w：std_logic_vector（4 DOWNTO 0）; 开始 row_w：= W_addr（7 downto 3）; col_w：= W_addr（2 downto 0）;if（Clk'event和Clk ='1'）然后 if（W_en ='1'）然后 - 写 -存储（CONV_INTEGER（row_w），CONV_INTEGER（col_w））我试图用计数器来驱动我的地址信号（写地址，读地址）。问题是，计数器仅输出i，j和k，每3位，而地址需要8位输入。我不允许更改组件的代码，所以我想知道是否有办法将i，j和k组合到端口映射中的地址。以上来自于谷歌翻译以下为原文 For my assignment, I have to connect a counter to the register file. Obviously, this is not the full code, I've only included the components: Counter:Library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_misc.all;use IEEE.std_logic_arith.all;Entity Counter isGeneric ( Delay:Time := 8 ns );Port ( Clk : In std_logic; Inc : In std_logic; Rst : In std_logic; i : Outstd_logic_vector(2 downto 0); j : Outstd_logic_vector(2 downto 0); k : Outstd_logic_vector(2 downto 0) );End Counter;Architecture BEHAVIORAL of Counter isBegin P: Process ( Clk ) Variable Value : UNSIGNED( 8 downto 0 ) := "000000000"; Beginif( Clk'event and Clk = '1' ) then if( Rst = '1' ) then Value := "000000000";elsif( Inc = '1' ) then Value := Value + 1;End if;End if; i(2)
2018-11-07 11:34
在汇编程序中，宏中有一些奇怪的问题。当我使用宏编译器说“错误（876）语法错误”时，当宏体直接写入代码时，没有错误。这可能是因为我在宏中使用3级宏吗？那么错误的真正原因是什么呢？谁知道呢？最好的问候，幼珍。 以上来自于百度翻译 以下为原文 HelloHave some strange trouble in assembler source, in macro. When i use macros compiler says "error(876) syntax error", when write the macro body direct to code, there is no error. May be this happens cause i use 3 level of macro in macro? movfl macro freg,litmovlw litmovwf fregendm;------------------------------------------------------------------------------movfl16 macro freg,litmovfl freg,Low(lit)movfl freg+1,High(lit)endm;------------------------------------------------------------------------------movfl32 macro freg,litmovfl16 freg,(lit & 0x0000FFFF)movfl freg+2,(lit >> 0x10) & 0xFFmovfl freg+3,(lit >> 0x18)& 0xFFendm;------------------------------------------------------------------------------_func: movfl16 ax, (0x4503114F & 0x0000FFFF) // this 3 lines works fine movfl ax+2,(0x4503114F >> 0x10) & 0xFF movfl ax+3,(0x4503114F >> 0x18)& 0xFF movfl32 bx, 0x4503114F // this macro cause an errorSo whats the real reason of error? Who knows? Best regards, Eugene.
2019-07-24 10:57
我正在用VHDL编写FFT算法，我需要进行一些位反转。似乎在没有编写附加功能的情况下执行此操作的唯一方法是在“循环”中执行此操作，即逐个重新分配/重新连接位，如下所示：rev_order“110”这给了我完美的结果 - 它快速且没有复杂的逻辑。现在来问题：正如您所看到的，我已经反转了3位，这对于8点FFT是足够的，但是如果点数将高于8，则需要手动添加额外的“nat_order（x）”信号。我正在尝试制作我的设计尽可能灵活，这种方法不会使它非常通用，即灵活，除非可以按GENERIC方式添加位，具体取决于点数，即如果address_width = 4，即16点..rev_order是否有可能以通用方式添加额外的信号？是否有其他方法可以非常快速地实现相同的位反转结果？亲切的问候，巢穴以上来自于谷歌翻译以下为原文I’m writing an FFT algorithm in VHDL and I need to do some bit-reversal. It seems that the only way to do it without writing an additional function, which would do it in a “looping”-way, is to re-assign/re-wire the bits one by one, like this: rev_order“110”This gives me the perfect result - it’s fast and no complicated logic behind it. Now to the problem: As you can see, I’ve reversed 3 bits, which is sufficient for 8 point FFT, but would require additional “nat_order(x)” signals be added manually if the number of points would be higher than 8. I am trying to make my design as flexible as possible and this method does not make it very generic, i.e. flexible, unless it’s possible to add the bits in the GENERIC fashion, depending on the number of points, i.e. if address_width = 4, i.e 16 points.. rev_order
2019-04-12 14:01
我有2台不同的计算机应该支持Optane内存：1.戴尔笔记本i5-8250U 12GB内存，1TB 5,400rpm硬盘2.惠普台式机i7-7700 16GB内存，2TB 7,200rpm硬盘每个都有一个开放的M.2插槽可供使用。我可以添加Optane内存模块，也可以添加NVMe SSD驱动器。我最好添加Optane或SSD吗？非游戏用途。 Optane添加量将是SSD成本的1/3。如果我添加Optane，我可以使用16GB或32GB模块。我认为处理器仅限于32GB内存，但这种限制是否仍然适用于额外的Optane？TIA以上来自于谷歌翻译以下为原文I have 2 different computers that are supposed to support Optane memory:1. Dell Notebook i5-8250U 12gb memory, 1TB 5,400rpm HDD2. HP Desktop i7-7700 16gb memory,2TB 7,200rpm HDDEach has an open M.2 slot to use.I can either add an Optane memory module or I'll add a NVMe SSD drive.Am I better off adding the Optane or the SSD?Non-gaming use.The Optane add would be 1/3 of the cost of the SSD.If I add the Optane, I can go with a 16GB or 32GB module.I think the processor is limited to 32GB memory, but does this limitation still apply to the additional Optane?TIA
2018-10-22 11:25
/tensorflow-lite/third_party/cmsis/CMSIS /NN/Source/ConcatenationFunctions/arm_concatenation_s8_w.o 。/eiq
2023-04-11 07:26
“Sordon Stefan”写道：>你好。>>我有2个Arrays-1D，我喜欢把它变成1个Array-2D。>>使用Matlab-Formular-Box我写X = [Array1 Array2]。>>但是如何在没有使用Matlab的情况下在VEE中使用？使用[Array1，Array2] [Array1 Array2]的公式在VEE5和之前工作但是逗号为VEE 6Stan
2019-10-31 13:30
