請問各位大神這題的解答是D嗎?我是因為最後的Tunnel Mode是concatenating才選的有大神可以幫忙解答正確答案嗎?感謝
2020-06-05 09:11
that the concatenating the commands to one line does work: *Version 3:* s.write('VOLT 2;*OPC?\n') result
2018-09-29 17:27
你好，我正在研究一个VHDL项目，我需要将两个数字相乘，M1 et M2。M1在8位上定义为带符号的定点数：“0 0.000000”M2是16位有符号整数“0 000000000000000”从数学上讲，乘法的答案应编码为24位（“0 00000000000000000000000”）在VHDL中，我们可以将两个长度不相同的数字相乘吗？如果没有，我们必须用符号位扩展最小值。M1'它会产生32位的乘法结果（M1'xM2），但24个足以编码“真实”结果......因此，我试过：Res：std_logic_vector（23 downto 0）; ...RES但在这种情况下，我在合成中发出警告，告诉我有一个长度不匹配...然后我写道：实体Synchro_voies是 港口 （Clk：在std_logic中; 拉兹：在std_logic;M1：在std_logic_vector（15 downto 0）;M2：在std_logic_vector（7 downto 0）;Res：在std_logic_vector（23 downto 0））;结束Synchro_voies;建筑行为的Synchro_voies是信号Res1：std_logic_vector（31 downto 0）;开始Res'0'）;elsif Clk'event和Clk ='1'然后 RES1但在这种情况下，Res1注册人是强制/有用的???亚历克斯以上来自于谷歌翻译以下为原文Hello, I am working on a VHDL project, in which i need to multiply two numbers, M1 etM2. M1 is defined on 8 bits as a signed fixed point number : "0 0.000000"M2 is a 16 bits signed integer "0 000000000000000" Mathematically speaking the answer of the multiplication should be coded on 24 bit ("0 00000000000000000000000") In VHDL, can we multiply two numbers that do not have the same length? If not, we must then extend the smallest with its sign bit. M1'
2019-01-14 13:54
大家好，我正在使用SPC56EL60L3和SPC5Studio。我注意到，有时我的应用程序卡住了，我发现，使用调试器，原因是触发了未处理的异常。由于它是随机发生的（或者，至少，我还没有发现任何模式），我无法弄清楚原因是什么。查看文档，我不清楚未处理的异常的原因是什么。任何人都可以分享一些细节吗？谢谢。亚历山德罗以上来自于谷歌翻译以下为原文 Hello everyone,I'm working with a SPC56EL60L3 and SPC5Studio.I noticed, sometimes my application got stuck and I found out, using the debugger, that the cause was an unhandled exception being triggered. Since it happens randomly (or, at least, I don't have identified any patterns, yet), I can't figure out what the cause is. Looking at the documentation it is not clear to me what the cause for unhandled exception could be. Can anyone share some details on this?Thank you.Alessandro
2019-07-02 07:37
嗨，大家好，我必须将CMOS传感器与Spartan6 FPGA接口。该传感器输出2通道LVDS 10位数据，480MHz和LVDS DDR时钟。当没有抓取时，传感器在其数据线上永久地输出IDLE字，这个词是已知的。这是我第一次使用IOSERDES，但我在Xilinx FPGA设计方面有足够的经验。首先，我认为适应XAPP1064很容易，因为它似乎提供了我需要的所有东西。但是在花了将近14天的时间来理解和模拟它之后，它确实让我疯狂。我已经阅读了XAPP-pdf和-source，SelectIO-Resources以及有关XAPP1064的几个论坛帖子。特别是“鲍勃·埃尔金德”和罗伊正在讨论很多bitlip的内部功能，我真的不明白这一点......需要为我需要的10：1因素服用4个ISERDES以及这一切是如何起作用的确让我发疯并且让我几次在桌子上用力捶打:-(认真：正如鲍勃所说，我试图将整个问题分成几部分。我想要开始的地方是忽略数据线，只关注时钟，延迟和PLL。所以我使用了“serdes_1_to_n_clk_pll_s16_diff”并用我的LVDS时钟（DDR，240MHz）提供它。在XAPP中，它们使用像B“1100001”这样的成帧字来通过时钟线传输，因此模块的“模式”输入设置为该字。但是我应该如何配置此输入，我的方案中没有框架字。如果我将其设置为B“01_0101_0101”，则bitlip FSM不会停止，因为有多次“模式”匹配。我应该如何对待我的DDR输入时钟？只是为了理解，请纠正我，如果我的以下假设不正确：“模式”输入应该在理想的定时点定义反序列化时钟的字，应该对数据进行采样？如果没有像我的场景中的框架时钟，这是行不通的？我的设置是XAPP pdf中的“案例2”或“图2”。源文件类似于第2页的“案例1”或“图1”。在我的情况下，必须在传感器的“空闲”数据字上完成“框架”或“训练”或“设置延迟”（不知道如何准确说出），这是已知的。当数据的ISERDES输出正确的IDLE字时，数据正确移位。从基本的理解：我的场景不应该需要ISERDES的时钟输入，是吗？LVDS输入的时序如下（仅用于说明，当然线路是差分的，有两条数据线）：如果有人提示，我可以如何继续或在哪里获得有关我的问题的更多信息，那将是很棒的。非常感谢，哈拉尔德。PS：如果在XAPP中添加16个serdes-factor文件的顶级示例和测试平台，就像在另一个线程中已经提到的那样，这将非常有用。以上来自于谷歌翻译以下为原文Hi everyone,I have to interface a CMOS sensor with an Spartan6 FPGA. The sensor outputs 2 lanes of LVDS 10bit-data at 480MHz and a LVDS DDR clock. The sensor permanentely puts out an IDLE word on its data line when not grabbing, this word is known. This is my first time using IOSERDES, but I've got adequate experience in Xilinx FPGA design. First I thought it would be easy to adapt the XAPP1064, because it seemed to deliver all the things I need. But after spending almost 14 days understanding and simulating it, it really drives me nuts. I've read through the XAPP-pdf and -source, SelectIO-Resources and several Forum threads here regarding the XAPP1064. Especially "Bob Elkind" and Roy were discussing a lot of the internal functionality of bitslip, where I really don't get the point out of it...The need of taking 4 ISERDES for the 10:1 factor I need and how this all works really drives me crazy and is getting me hitting my head hard on the table several times :-( Seriously:As Bob mentioned, I tried to divide the whole problem into parts. Where I want to start is ignoring data lines at the moment, just looking at clocks, delays and PLL's. So I've used "serdes_1_to_n_clk_pll_s16_diff" and fed it with my LVDS clock (DDR, so 240MHz). In the XAPP, they use a framing word like B"1100001" to transmit over the clock lines, so the "pattern" input of the module is set to this word. But how should I configure this input, I don't have a framing word at my scenario. If I set it to B"01_0101_0101", then the bitslip FSM don't stop, because there are multiple times, where the "pattern" matches. And how should I treat my DDR input clock? Just for understanding, please correct me, if my following assumptions are not correct:The "pattern" input should define the word of the de-serialized clock at the ideal timing point, where data should be sampled? This can't work without a framing clock like in my scenario?My setup is "Case 2" or "figure 2" in the XAPP pdf. The source files are like "Case 1" or "figure 1" on page 2.In my case, the "framing" or "training" or "setting up the delay" (don't know how to say exactly) has to be done over the "IDLE" data word of the sensor, which is known. When the ISERDES of the data puts out the correct IDLE word, the data is shifted correctly.From the fundamentally understanding: My scenario shouldn't need ISERDES for the clock inputs, does it? The timing of the LVDS inputs look like follows (just for illustration, of course the lines are differential and there are two data lines): It would be great if someone has hints, how I can proceed or where I've got more information about my problem. Thanks alot,Harald. PS: It would be really helpful, if top-level examples and testbenches for the 16-serdes-factor files would be added in the XAPP, like already mentioned in another thread.
2019-07-16 07:44
驱动程序的通用选项有哪些？NAND FLASH芯片的属性是什么？有哪些应用？
2021-07-27 07:36
