。 clockGen1.jpg Web 界面可以轻松选择参数。 输出在 GPIO03 (RX0) 上，可以直接使用，但我通过 74LVC2G34 双驱动器缓冲我的驱动器以增强驱动能力。 详情请访问https://github.com/roberttidey/espI2sClockGen
2023-05-22 07:34
Host clock产生：见eth_clockgen.v代码，应该是没有错的啊？求各路大神指点啊？到底是哪儿出错了还是代码需要在哪儿修改什么的？
2013-05-11 14:11
, ECC on) caam_jr: caam not found Initialized clockgen Using SERDES1 Protocol: 60248 (0xeb58) PCIe2
2023-06-02 10:57
本文根据所设计的音频控制器的结构详细介绍了构建SoC内核仿真环境来测试音频控制器的思想和实现方法。
2021-06-07 07:07
大家好，我有一个用Spartan 3E控制HV脉冲的设备。使用赛普拉斯的GPIF协议寻址多达512个寄存器和外部SRAM，与外部PC和存储器进行通信。时钟系统基于两个不同的外部时钟：48MHz控制GPIF通信和50MHz。我还使用DCM（由48MHz时钟驱动）创建270度移位时钟，以获得正确的信号读/写成一些静态SRAM和另一个DCM创建一个20MHz时钟（从50MHz时钟）来控制脉冲的产生。问题是，有时由于HV产生的噪声，我不再能够读取寄存器，并且我读取所有寄存器地址的相同值。即便在这一刻，20MHz时钟仍能正常工作。我想这个问题是由于48MHz DCM冻结，因为重置fpga一切都恢复正常。这有可能吗？如果是，请问您是否有任何关于如何避免冻结DCM或如何自动重置的建议？如果没有，你对如何解释这种行为有任何想法吗？外部时钟始终有效。非常感谢克劳迪奥以上来自于谷歌翻译以下为原文Hi all,I have a device controlling HV pulses with a Spartan 3E. The communication with an external PC and memories is done using the GPIF protocol from Cypress addressing up to 512 registers and an external SRAM. The clock system is based on two different external clocks: a 48MHz controlling the GPIF communication and a 50MHz. I also use a DCM (driven by the 48MHz clock) to create a 270 degree shifted clock to obtain correct signals to read/ write into some static SRAM and another DCM to create a 20MHz clock (from the 50MHz clock) to control the pulse generation. The problem is that sometimes due to the noise generated by the HV I'm no longer able to read the registers and I read always the same value for all the register addresses. Even in this moment the 20MHz clock continues to work properly. I guess this issue is due to the freeze of the 48MHz DCM because resetting the fpga everything is resumed and works properly.Is it possible this?If yes, please, do you have any suggestion about how to avoid a freeze of the DCM or how to reset it automatically?If not, do you have any idea about how to explain this behavior? The external clock is always working. Thanks a lotClaudio
2019-07-19 12:49
音频控制器的结构和原理是什么？SOC仿真环境的构成和原理是什么？
2021-06-04 06:40
