您能否提供 BFU660F 的 spice 模型？
2023-04-21 09:04
我正在使用 STM32Cube_FW_WL_V1.0.0 开发一个项目。我无法编译包含在 BFU_1_Image 示例项目中的 1_Image_SECoreBin 项目。我在 macOS
2023-01-05 08:10
您好，我的名字是Bontor。我正在尝试在Digilent Atlys板上实现我的HDL设计（fft模块），该板使用Spartan 6作为FPGA内核。你的电路板提供100 MHz时钟，而我的设计只能以18 MHz运行。所以我使用DCM coregen模块将时钟降低到18 MHz。问题是，DCM输出来自BUFG，在我的设计中，时钟信号用于驱动某些多路复用器，作为选择器输入。当我直接将DCM时钟输出连接到多路复用器选择器输入时，我得到错误：放置：1206，说“全局缓冲器实例，驱动网络，即驱动以下（前30个）非时钟源引脚脱离芯片。 “在这个论坛上阅读后，我发现了类似的问题：http://www.xilinx.com/support/answers/35032.htm解决方案是使用ODDR2实例化（时钟转发技术），其中时钟信号不直接驱动负载引脚，而是充当ODDR2的输入，然后ODDR2的输出用于驱动引脚。我尝试在我的设计中实现这个，但它失败了，说“ERROR：Pack：2530- 双数据速率寄存器无法根据需要加入anOLOGIC组件。”这是明确的，因为我使用ODDR2输出来驱动内部信号而不是输出引脚（我意识到ODDR2输出必须驱动输出引脚来自http://forums.xilinx.com/t5/Virtex-Family-FPGAs/problem-with- ODDR-集团/ TD-p / 105919）所以，我需要一个关于如何使用DCM模块输出来驱动内部引脚的解决方案（在这种情况下，mux输入）。是否有类似ODDR2的模块，但输出可用于内部信号？我一直试图在过去的7个小时内解决这个问题，请帮助我。任何帮助将不胜感激。以上来自于谷歌翻译以下为原文Hello my name is Bontor. I am trying to implement my HDL design (fft module) in Digilent Atlys board that use Spartan 6 as FPGA core. Thee board supply 100 MHz clock while my design can only run at 18 MHz. So I use DCM coregen module to reduce the clock to 18 MHz. Problem is, DCM output is from a BUFG, and in my design, the clock signal is used to drive some mux, as selector input. When I straightforwardly connect DCM clock output to the mux selector input, I get the ERROR:Place:1206, saying" the global buffer instance, driving the net, that is driving the following (first 30) non-clock source pins off chip." After reading on this forum, I found similar problem in:http://www.xilinx.com/support/answers/35032.htm The solution is to use ODDR2 instantiation (clock forwarding technique), where the clock signal does not drive the load pin directly, instead act as input to ODDR2, then the output of ODDR2 is used to drive the pin. I tried to implement this in my design, but it failed,, saying "ERROR:Pack:2530 - The dual data rate register failed to join an OLOGIC component as required.". Which is clear because I used the ODDR2 output to drive internal signal instead of an output pin (I realize ODDR2 output must drive output pin from http://forums.xilinx.com/t5/Virtex-Family-FPGAs/problem-with-ODDR-bloc/td-p/105919) So, I need a solution on how to use output of DCM module to drive internal pin (in this case, mux input). Is there similar module like ODDR2, but the output can be used in internal signal? I have been trying to solve this in the last 7 hours, please help me. Any help would be greatly appreciated.
2018-10-17 14:28
new interface driver bfu***Bluetooth: Generic Bluetooth USB driver ver 0.6u***core: registered new
2018-06-04 09:39
