以下为原文I am in the process of updating our test benches to new DAQ, GPIB, and VEE 9.32. I have
2018-10-10 17:44
and different benches but they still fail.What should I look for next?
2018-10-19 11:39
您好，我正在从rfde更新到goldengate以获得节奏，并且正在查看包含的库adsLib。我注意到库是不同的，并且rfde中的单元格不在goldengate中，例如源或数据项？感谢您的任何意见。加布里埃尔 以上来自于谷歌翻译 以下为原文Hello, I am updating to goldengate from rfde for cadence and was looking though the included library, adsLib. I noticed that the libraries are different and cells that are in rfde are not in goldengate such as sources or data items? Thanks for any input. Gabriel
2018-12-29 16:36
Verilog test benches into one ISE project file as follows: When I try to run a simulation using
2019-03-06 11:35
你好，到目前为止，我一直在使用10.1 SP3 xilinx版本。当我切换到11.1版本并寻找如何将“测试工作台wavefors”作为我的设计的输入时，我没有看到tat选项....我看到“VHDL测试台”......这不是我想要的。“测试台波形”选项直接为我们提供了手动输入波形作为输入的选项.....我想在11.1中进行操作...我如何到达那里？我的Q非常基本，但我很遗憾我只是学习使用xilinx和VHDL的新功能......谢谢。以上来自于谷歌翻译以下为原文Hello, I have been using 10.1 SP3 xilinx version till date. When i switch to 11.1 version and look for how to give the "test bench wavefors" as input to my design, i dont see tat option.... i see"VHDL test bench"...which is not what i want. "test bench waveforms" option directly gives us an option to manually give the waveforms as input.....I want to do tat in 11.1... How do i get there? My Q mught be very basic but I am sorry i m just learning to use xilinx and new to VHDL too... Thank you.
2019-01-16 07:52
我们在模拟功率放大器的EVM方面遇到了问题。请帮助。感谢你Dipankar Vedant 以上来自于谷歌翻译 以下为原文We are facing problem in simulating EVM for a power amplifier. Kindly help. Thanking youDipankar Vedant
2018-10-12 17:15
大家好我想知道关于FPGA需要了解的内容，因为入门套件会很好（低成本！）和相关的书籍/文档。我也想学习VHDL。我在电子学和编程方面经验丰富，在2000年我使用Xilinx Spartan使用Xilinx Foundation进行了设计（原理图捕获），我不得不接触VHDL。我当时承受了巨大的压力以便设计出来，所以没有机会正确地学习它，但现在我已经有了。我想用FPGA来制作复古的东西，没什么好看的。让旧的SCSI控制器（W033C93A）已经建立起来是好的，所以我可以将它们用作模块。提前致谢以上来自于谷歌翻译以下为原文Hi all I would like suggestions on what I need to learn about FPGA, as what starter kit would be good (low cost pls!) and relevant books/documentation. I want to learn VHDL too. I am quite experienced in electroncs and programming, in 2000 I did a design using a XCS20 Spartan using Xilinx Foundation (schematic capture), I had to sub-contact the VHDL. I was under a huge amount of pressure at the time to get a design out so didn't really have chance to learn it properly, but now I have. I want to use a FPGA for retro stuff, nothing really fancy. It would be good to have old SCSI controller (W033C93A) already implimented so I could use them as modules. thanks in advance
2019-01-11 10:37
采用正交频分多路转换（OFDM）实体层的无线区域网路（WLAN），目前已经在全球各地广泛地进行商业建置，它主要是根据IEEE 802.11a/g OFDM 无线电标准。现在设计工程师正使用移动无线平台专用的多模态IEEE 802.11a/b/g 晶片组，来提升IC 整合的程度，以配合价格低廉的无线上网服务。新兴的IEEE 802.15.3a超宽频（UWB）和IEEE 802.16d 无线都会区域网路（WMAN, 又称WiMAX）标准，将促使IC 设计朝更高资料速率的OFDM 应用发展。
2019-07-16 08:11
我正在使用Xilinx ISE Ver 6.1I我已经编写了许多程序和测试，程序运行正常并给我RTL Schematics以及他们的测试结果。我已经写了他们的测试，但我怎么能检查我的测试台的代码。例如，这是代码//数据流和带两个输入模块的门模块和2（x1，x2，z1）;输入x1，x2;输出z1;线x1 ，x2;导线z1;分配z1 = x1＆amp; x2; endmodule ***********************************和这个测试bench1 //和2测试benchmodule和2_tb; reg x1，x2; 5线z1; //显示变量初始$ monitor（“x1 =％b，x2 =％b，z1 =％b”，x1，x2，z1）; 10 //应用输入矢量初始值＃0 x1 = 1 'b0; x2 = 1'b0; 15＃10 x1 = 1'b0; x2 = 1'b1;＃10 x1 = 1'b1; 20 x2 = 1'b0;＃10 x1 = 1'b1; x2 = 1 'b1; 25＃10 $ stop; end //将模块实例化为test benchand2 inst1（30 .x1（x1），。x2（x2），。z1（z1））; endmodule ******** *******************************我如何检查测试并查看Xilinx ISE中的波形以上来自于谷歌翻译以下为原文I am using Xilinx ISE Ver 6.1I have written many programms and test bences in itThe programms are running fine and give me RTL Schematics as wellBut what abt their test bences. I have written their test bences but how can i check the code of my test bench.For example this is code//dataflow and gate with two inputsmodule and2 (x1, x2, z1);input x1, x2;output z1;wire x1, x2;wire z1;assign z1 = x1 & x2;endmodule***********************************and this test bench1 //and2 test benchmodule and2_tb;reg x1, x2;5 wire z1;//display variablesinitial$monitor ("x1 = %b, x2 = %b, z1 = %b", x1, x2, z1);10 //apply input vectorsinitialbegin#0 x1 = 1'b0;x2 = 1'b0;15#10 x1 = 1'b0;x2 = 1'b1;#10 x1 = 1'b1;20 x2 = 1'b0;#10 x1 = 1'b1;x2 = 1'b1;25 #10 $stop;end//instantiate the module into the test benchand2 inst1 (30 .x1(x1),.x2(x2),.z1(z1));endmodule***************************************how can i check test becnh and see waveforms in Xilinx ISE
2019-01-17 06:05
—Settings—Simulation，查看仿真工具以及语言是否与之前一致否则进行相应修改。选中Compile test bench单击Test Benches后点击OK。可以看到如图2-10界面。图2-10-1
2019-01-24 01:54
