February 2012, we received a number of real-time questions from a broad audience. If one person asks
2019-09-10 15:01
全球领先的传感器供应商InvenSense（INVN)7日宣布收购法国运动处理技术公司Movea,旨在通过此次收购在运动传感器和联网式（GPS/WIF）数据追踪技术方面得以提升，此项收购的规模为8100万美元，其中现金部分为7500万美元。
2020-04-28 06:14
嘿。如何将sdk grid 2.0芯片送到Maxwell？目前，我们的团队正在开发基于GRID SDK版本2.3的平台：2014年4月2日，用于芯片Kepler。以上来自于谷歌翻译以下为原文Hey. how to get the sdk grid 2.0 chips to Maxwell? At the moment our team is developing a platform based on GRID SDK Version 2.3: April 2, 2014 for chips Kepler.
2018-09-11 16:29
and mixed-signal IC design targeting the audience of electrical engineers, company managers and marketing engineers
2015-09-25 10:22
什么是SoC？SoC是由哪些部件组成的？
2021-10-19 06:29
SoC是什么意思？SoC是由哪些部件封装组成的？
2021-10-19 06:07
我试图编译我们的Mplabs（V3.61）项目直接在Matlab（2013B），以使构建过程更容易。我可以直接编译在MPLABS没有问题。我也可以使用命令行编译，没有问题。问题是在通过Matlab调用命令行时出现的。由于受限的LiceNeS访问Microchip，选择了一个新的密钥。我们有一个网络许可证，并且没有直接使用MPLAB或CMD窗口的许可证问题。我在Matlab中尝试过：CT/MaFix-VCuM.Cpff.Mk子项目=。构建“CON-F NBPoCT/MaFix-VCuMYCCPF.MK子项目=。构建CONF’，’-ECHO’）；Win OnLead（“Buff.BAT”）//Buff.BAT包含命令行，它们都会产生许可证错误。我已经尝试漫游网络许可证，它是直到出错，我做错了什么？谢谢你的帮助。 以上来自于百度翻译 以下为原文 I am trying to compile our Mplabs (v3.61) project directly in Matlab(2013b) to make the build process easier. I can compile directly in Mplabs with no issue. I can also compile using the command line without problem either. The problem arises when calling the command line through Matlab. Options have been disabled due to restricted licenseVisit microchip to purchase a new key. We have a Network license and there’s no license problem directly using Mplabs or the cmd window. I have tried in Matlab:system('make -f nbproject/Makefile-VCU_m_ccpf.mk SUBPROJECTS= .build-conf', '-echo');dos('make -f nbproject/Makefile-VCU_m_ccpf.mk SUBPROJECTS= .build-conf', '-echo');winopen('build.bat') //with build.bat containing the command line They all come up with the license error.I’ve tried roaming the network license out, it still comes up with the error.What am I doing wrong?Thanks for your help.
2018-12-11 15:42
大家好，在我的设计中，spartn6有一个TI收发器tlk2211接口，它以ddr模式发送数据（RD），并采用两个反向clk（RBC0 / 1）来捕获每个上升沿中的数据。附件中显示的波形，我有点困惑，我应该如何捕获数据并同步到内部时钟？有没有办法将两个时钟合并到一个时钟信号并用这个时钟捕获数据？谢谢，加斯以上来自于谷歌翻译以下为原文Hi all, In my design there is a TI transcever tlk2211 interfaces to spartn6, which send data(RD) in ddr mode, and sourced with two inverted clk(RBC0/1) to capture the data in each of the rising edge. the waveform asshown in the attachment, I'm a little puzzled how should I capture the data and sync to the internal clock?is there any way to merge the two clock to a signle clock and capture the data with this clock? Thanks,Gauz
2019-06-19 09:16
嗨， 我想把晶体振荡器的CLK带到FPGA里面的数字设计。该CLK连接到FPGA的I / O引脚。如果我在映射中运行Impliment设计，我将得到错误。所以我将在UCF文件中将网名命名如下。NET“clk_i”LOC =“P4”| IOSTANDARD = LVCMOS33 | CLOCK_DEDICATED_ROUTE = FALSE; 有一段时间它会起作用。之后它无法正常工作。 如果我从内部获取CLK，则相同的数字设计正常工作（即高频CLK从GCLK引脚进入并将其分配给数字设计）。有没有与clk相关的问题？感谢你，Mahesh Hegde。以上来自于谷歌翻译以下为原文Hi,I want to take CLK from Crystal oscillator to my digital design inside FPGA. This CLK is connected to I/O pin of FPGA. If i run Impliment design in mapping i will get error.So i will name the net as like as follows in the UCF file.NET "clk_i"LOC = "P4" | IOSTANDARD = LVCMOS33| CLOCK_DEDICATED_ROUTE = FALSE; For some time it will work. after that it is not working.Same digital design working properly if i take CLK from internally (i.e High frequency CLK is entering from GCLK pin and will devide it give it to the digital design ). Is there any clk related issue?Thanks You in Advance,Mahesh Hegde.
2019-01-29 10:05
嗨，我使用Xtreme DSP spartan3a DSP 1800a板。我想设置bank I / O电压的值？我怎么能这样做？请给我一些建议，并提供一些适当的手册。谢谢以上来自于谷歌翻译以下为原文Hi, I use Xtreme DSP spartan3a DSP 1800a board. I want to set the value of bank I/O voltage? How I can do that? please give me some advice and sugest some appropriate manual. thanks
2019-06-17 08:40
