have seen anything in there regarding this issue. I believe I have given the unit ample time to warm
2019-07-24 09:56
implemented in the PCB design (ample decoupling caps, 4-layer PCB, optical isolation of signals
2018-10-12 16:31
本文介绍了MN34041 NanoVesta摄像头主要特性和详细电路图。
2021-06-02 06:42
嗨，我有一个Windows Server 2003和raid配置。我附上了英特尔存储PC的快照和系统报告的详细信息。从附件中，您将看到PC正在尝试重新构建第二个RAID驱动器。不幸的是，重建不成功，PC今天早上又失败了。这是我们尝试重建的第三个驱动器，作为良好驱动器的合作伙伴。 PC在一个驱动器上运行一段时间，但最终会在没有警告或重新构建伙伴驱动器的情况下失败。因此，我们认为问题不在于驱动器，而在于RAID配置，英特尔软件或PC中的硬件。请一些人试着帮我解决这个问题。问候，KARTHIK报告System29082018.txt.zip 1.2 K. 报告Storage Manager29082018.txt.zip 1.2 K. Port 3 Information.JPG 93.6 K.Port 1 Information.JPG 91.3 K.基本观点.JPG 72.9 K.以上来自于谷歌翻译以下为原文Hi, I have a windows server 2003 and raid is configured. I have attached the snapshots of the Intel storage PC and details of the system report. from the attachments, You will see that the PC was trying to re-build the second RAID drive. Unfortunately, the re-build was unsuccessful and the PC was failed again this morning. This is the third drive we have attempted to re-build as a partner to the good drive. The PC runs OK on one drive for a while but eventually fails without warning or during re-build of the partner drive. We are therefore thinking that the problem is not with the drives but with either the RAID configuration, the Intel software or the hardware in the PC.Please some one try to help me out of this issue. Regards,karthik Report System29082018.txt.zip 1.2 KReport Storage Manager29082018.txt.zip 1.2 KPort 3 Information.JPG 93.6 KPort 1 Information.JPG 91.3 KBasic view.JPG 72.9 K
2018-11-19 14:16
您好，我正在尝试使用PXA信号分析仪测量多载波基站发射机的ACP。载波间隔为1MHz，有6个载波具有GMSk调制。每个载波的功率为36.4 dBm。在载波配置的ACP设置中，有一个名为“Measurement Noise BW”的按钮。这个BW有什么意义？这是测量电枢功率的BW吗？我的载波BW是200 KHz（GMSK）。但是将测量噪声BW分成200KHz，每个载波的测量功率比预期的36.4dBm小约1.5dB。为了获得36.4 dBm的载波功率，测量带宽应该在1MHz左右？这也与“Integ BW”和“RRC加权”的测量方法有关。请解释这些方法之间的区别。谢谢Leyo 以上来自于谷歌翻译 以下为原文Hello, I am trying to measure the ACP of a multi-carrier basestation transmitter using PXA signal anlyzer.The carriers are spaced @ 1MHz and there are 6 carriers with GMSk modulation. Power of each carrier is 36.4 dBm.In the ACP setup for carrier configurations, there is a a button called "Measurement Noise BW". What is the siginificance of this BW. Is this the BW in which the acrrier power is measured?. My carriers BW is 200 KHz(GMSK) . But seeting the measurement noise BW to 200 KHz, the measured power of each carriers is around 1.5 dB less than the expected 36.4 dBm. To getcarrier power of 36.4 dBm, the measurement BW should be around 1MHz?Also is this tied to the measurment method of "Integ BW" and "RRC weighted".Please explain the difference between these methods. ThanksLeyo
2019-08-05 09:30
你好，我用SIM7600CE GSM模块作为设备，PIC32作为主机，GSM模块有USB接口（4个虚拟端口），我想和任何一个虚拟端口通信，我在MLA中没有找到多端口环境的源代码。
2020-03-09 06:59
我有一个实现了一个SPI接口的进程。所有输入都由相同的100MHz时钟同步，为时钟进程提供时钟。整个设计由同一时钟驱动和约束。满足时序（除了这里没有涉及的一些EMIF总线问题）。一切正常，除了32位味噌结果的m***错误~50％的时间。我已经将信号（包括miso信号的内部版本和miso移位寄存器的l***）移植到连接到逻辑分析仪的引脚。位计数器（dsmspi_xfer_cnt）始终是正确的内部味噌（dsmspi_miso）总是正确的。移位寄存器的l***是发生错误的地方。请参阅附件中的以下行：elsif dsmspi_sclk_base_d1 ='1'且dsmspi_sclk_base_d2 ='0'且dsmspi_xfer_ce ='1'则dsmspi_dataout dsmspi_datain dsmspi_xfer_cnt结束if;我很难过！提前致谢。dsm_spi_iface.vhd 14 KB以上来自于谷歌翻译以下为原文I have a process that implements an SPI interface.All inputs are synchronized by the same common 100MHz clock that clocks the process.The entire design is driven and constrained by the same clock.The timing is met (except for some EMIF bus issues which are not involved here). Everything works except the m*** of the 32 bit miso result is wrong ~50% of the time. I have ported signals, including the internal version of the miso signal and the l*** of the miso shift register, to pins connected to a logic analyzer.The bit counter (dsmspi_xfer_cnt) is always correctThe internal miso (dsmspi_miso) is always correct.The l*** of the shift register is where the error occurs. See the following line in the attached file:elsif dsmspi_sclk_base_d1='1' and dsmspi_sclk_base_d2='0' and dsmspi_xfer_ce='1' then dsmspi_dataout
2019-07-01 11:17
你好我正在使用Xilinx Spartan3E入门套件。我可以单独控制ADC和DAC部件，但是我无法将两个模块连接在一起。直通系统不起作用。我想找到类似的代码与我的相比较但我只是找到了信号发生器的picoblaze代码。我想知道Xilinx是否为ADC和DAC提供了直接通过系统的样本代码。因此我可以从中找到并在我的代码中找到错误。 或者任何在ADC和DAC直通系统中取得成功的人都可以给我一些建议。 大卫以上来自于谷歌翻译以下为原文HiI am working with the Xilinx Spartan 3E starter kit.AndI can controlthe ADC and DAC part seperately ,but I fail to connet two modules together.The straight-through system does not work.I would like to find the similar code to compare with mine.But I just find the signal generator picoblaze code. I wonder whether the Xilinx has provided any sample code for the ADC and DAC straight through system.Therefore I can learn from it and find theerror in my code.Or anyone who has succedded in ADC and DAC straight through system can give me some suggestions. David
2019-05-28 13:15
大家好。数据表显示LVCMOS25的最大VCCO为2.7V。我想为2.7V CMOS器件和Spartan-3 VCCO使用单个稳压器。现在将VCCO连接到2.7V是完全安全的吗？如果是，I / O会产生2.7V还是保持在2.5V？什么是更好的解决方案？谢谢你的回复。以上来自于谷歌翻译以下为原文Hello people.Datasheet says the maximum VCCO for LVCMOS25 is 2.7V.I want to use a single regulator formy 2.7V CMOS devices and Spartan-3 VCCOs. Now is it totally safe to tie VCCOs to 2.7V ??If yes, will the I/Os produce 2.7V or remain at 2.5V ?? What is a better solution ?? Thanks for any replies.
2019-05-20 08:55
我正在运行Spartan 6 block ram的模拟。时钟速度为100Mhz。块ram的写作运作良好。我可以在内存中看到数据。但是当我读取数据时，输出有2个时钟的延迟。在块ram用户guidt中，它只表示1个时钟延迟。如果有人能帮忙看看，我将不胜感激。我在这里附上了我的源代码和模拟快照。源代码：解压后请打开项目文件：.. \ study \ par \ opcode \ opcode.xise。屏幕简短说明：数据在地址0处为0x09，在地址1处为0x13，在地址2处为0xa，在地址0x3处为0x14。从模拟开始，它具有2个时钟延迟，以便在上升时钟呈现地址后获得正确的数据输出。提前致谢！方study.zip 3795 KB以上来自于谷歌翻译以下为原文I am running a simulation of Spartan 6 block ram. The clock speed is 100Mhz.The writing of block ram is working well. I can see the data in memory.But when I read the data the output has 2 clocks of latency. In block ram user guidt it says only 1 clock latency.I will appreciate if anyone can help to look at it. I attached my source code and simulation snapshot here. Source code: After unzip please open the project file located at: ..\study\par\opcode\opcode.xise.Screen short explanation: The data is 0x09 at address 0, and 0x13 at address 1, 0xa at address 2, 0x14 at address 0x3.From the simulation it has 2 clocks latency to get correct data out after presenting address at rising clock. Thanks in advance! Fangstudy.zip 3795 KB
2019-07-25 08:15
