PQ208. I realise that it quite ambitious given that I have not designed a board with a FPGA before
2019-05-10 13:59
亲爱的大家我是fpga世界的新手。我设计了一块板子来试验spratan 3（XC3S400-5 TQFP 208）设备。并添加了一些costum外围设备（led，switch，max232 ......）。除了我的sdram部分，我的电路板的每个部分都正常工作。我已经将8MB SDRAM设备连接到芯片。我已经从pc100 32MB SDRAM模块拆除了sdram设备。该ram是16位宽。我在网上找到了几个sdram控制器，但是我无法存储或读取任何内容。我问的是你有没有改变sdram的工作代码并使它像sram那样我可以测试我的硬件？你有什么想法我怎么测试芯片是否存活？最好的祝福。我喜欢Digital和参与其中的你！以上来自于谷歌翻译以下为原文Dear allI'm new in fpga world.I have designed a costum board to experiment with spratan 3 (XC3S400-5 TQFP 208) device. and added some costum peripherals (led's, switches,max232...).every part of my board is working correctly except my sdram part.I have connected a 8MB SDRAM device to the chip.I have desolder the sdram device from a pc100 32MB SDRAM module.the ram is 16bit wide.I have found several sdram Controllers on net but i can not store or read anything from it.all that i'm asking is that do you have any working code that change the sdram and makes it like a sram so i can test my hardware? do you have any idea how can i test if the chip is alive? with best regards.I love Digital and you who involved in it!
2019-05-16 13:10
目前我使用的是MIDI输入的24FJ256GA108。我使用一个31250波特的串行端口，工作非常出色。（PIC处理MIDI命令并驱动/控制教堂的一个CARLLION），但是客户认为串行MIDI有点过时，需要USB。有人已经实现了吗？（我宁愿继续使用串行MIDI，因为它是好的和简单的…（但不是我的干系……微笑： 以上来自于百度翻译 以下为原文 At the moment I'm using the 24FJ256GA108 for MIDI input.I use one of the serial ports at 31250 baud, works excellent.(PIC processes Midi commands and drives/controls a church carillion) But client thinks the serial MIDI is a bit old fashioned, and wants USB.Has anybody implemented that already?(I rather would keep using serial MIDI, because it's nice and simple... (but not my desicion... Smile:)
2018-09-05 16:23
嗨，我想用E5071C测量我的2x2和4x4天线的VSWR，回波损耗，谐振频率。我想知道如何为MIMO应用设置E5071C。有设置图吗？有关网络分析的MIMO天线测量的具体应用说明？我想同时测试我的2x2和4x4天线。这是我的MIMO天线表征。我想验证每个天线是否会对彼此造成干扰，因为MIMO的切换速度比单天线快得多。 MIMO使用多个天线来满足从更宽角度接收信号的空间分集。希望你能帮忙。 以上来自于谷歌翻译 以下为原文Hi, I want to measure VSWR, return loss, resonant frequency of my 2x2 and 4x4 antenna using E5071C. I like to know how to setup E5071C for MIMO application. Is there a setup diagram? Any specific application note for MIMO antenna measurement on network analysis? I want to test my 2x2 and 4x4 antennas simultaneously. This is for my MIMO antenna characterization. I want to verify whether each antenna will cause interferences to one another as the switching speed for MIMO is much faster then single antenna. MIMO uses multiple antenna to cater for spatial diversity receiving signal from wider angle. Hope you can help.
2018-12-18 16:26
我是FPGA和Xilinx设计的新手。我目前正在使用赛灵思的Atlys主板和XAPP495 HDMI驱动程序。我正在使用Digilent'Atlys HDMI演示项目'应用程序，在将输出帧输出到HDMI输出端口之前，将每个视频帧存储在外部存储器中。我正在尝试使用HDMI源的动态背景进行色度键效果。我的想法是使用2个HDMI输入和1个HDMI输出。我想使用Atlys的两个HDMI输入并逐个像素地混合两个帧。然后将混合帧输出到HDMI输出端口。混合包括将第一个输入的每个像素值与阈值进行比较： - 如果它大于阈值，我想输出FIRST视频的像素值。 - 如果它低于该值，我想输出SECOND视频的像素值。然后，输出视频缓冲器由来自第一和第二HDMI输入的像素组成。输入和输出都具有相同的分辨率。我想知道这个实现是否可行。我想到了两个解决方案： 1.硬件搅拌机：在输入解码器和DDR2之间放置一个多路复用器块。该块接收来自两个输入的像素值（来自解码器块的输出），并将正确的值输出到存储在DDR2中的值。对于帧中的所有其他像素重复此操作。 1.使用micrlaze：使用处理器比较两个输入并输出混合帧，而不使用外部存储器帧存储。理想情况下，我想做硬件实现。是否有可能在3周内完成（总共20小时）？如果是这样，你有什么想法，如何输入像素块的多个输入块？谢谢！以上来自于谷歌翻译以下为原文I'm new to FPGA and Xilinx design. I'm currently using the Atlys board and the XAPP495 HDMI drivers from Xilinx. I'm using the Digilent 'Atlys HDMI Demo Project' application that stores each video frame in the external memory before outputing the frame in the HDMI output port. I'm trying to do a chroma key effect with a dynamic background from a HDMI source. My idea is to use 2 HDMI inputs and 1 HDMI output. I'd like to use both HDMI inputs of the Atlys and mix both frames pixel by pixel. The mixed frame is then output to the HDMI output port. The mixing consists in comparing each pixel value of the first input to a threshold: - If it's greater than the threshold, I'd like to output the FIRST video's pixel value. - If it's below the value, I'd like to output the SECOND video's pixel value.The output video buffer is then composed of pixels from the first and the second HDMI inputs. Both inputs and output have the SAME RESOLUTION. I'd like to know if this implementation is doable. I thought of 2 solutions: 1. Hardware mixer: Place a multiplexer block between the inputs decoders and the DDR2. The block receives the pixel values from both inputs (output from the decoder blocks) and outputs the correct value to the be stored in the DDR2. This is repeated for all the other pixels in the frame. 1. Using microblaze: Using the processor to compare both inputs and output the mixed frame, without using the external memory frame storage. Ideally, I'd like to do the hardware implementation. Is it possible to be done in like 3 weeks (20 hours total)? If so, do you have any ideas as HOW TO INPUT BOTH INPUT PIXEL VALUES TO THE MULTIPLEXER BLOCK? Thanks!
2019-07-04 06:28
大家好， 我有一个项目，目的是检测彩色图像。我正在使用Nexys4 FPGA和uCam-II作为我的相机。我的相机将通过UART与我的电路板通信，并通过nexys板的VGA输出显示在显示器上。 我一直在学习基本的verilog代码，比如在7 Seg显示器上使用开关控制它来实现和显示BCD计数器。 我不确定如何去做我的项目。谁能告诉我某个地方要开始？以上来自于谷歌翻译以下为原文Hi all, I have a project with the objective of detecting coloured images. I am using a Nexys4 FPGA and a uCam-II as my camera. My camera will be commnicating with my board via UART, and this will be displayed to a monitor via the VGA output of the nexys board. I have been learning basic verilog code like implementing and displaying a BCD counter on the 7 Seg Display using switches to control it. I am not sure how to go about doing my project. Can anyone tell me somewhere to start?
2019-04-12 14:38
大家好，我们计划基于Spartan6 75LX设备开发自己的主板。我想知道是否可以使用两个不同的MCB将两个不同的So-DiMM DDR2存储器连接到我们的电路板上？我的FPGA器件的多少引脚将用于使用So-DiMM连接两个存储器？我希望不是所有的2x200 :-)当然，我们的FPGA将消耗多少资源？亲切的问候，帕沃尔 - 布尔诺理工大学研究助理| RehiveTech衍生公司的首席执行官以上来自于谷歌翻译以下为原文Hello Guys, We are planning to develop our own board based on the Spartan6 75LX device. I'm wondering if it is possible to connect two different So-DiMM DDR2 memories to our board using two different MCBs? How many pins of my FPGA device will be used for connecting both memories using So-DiMMs? I hope not all 2x200 :-) And, of course, how many resources of our FPGA will be consumed? Kind Regards,Pavol--Research Assistant at Brno University of Technology | CEO at RehiveTech spin-off company
2019-05-28 09:05
目前，对于我的一位客户，我正在为新的XenApp主机编写新硬件设计。其中一个要求是用于图形加速的GPU。所有XenApp用户都是任务/知识工作者。我是GRID解决方案的忠实粉丝，但GRID 2.0 / 3.0中许可组件的额外成本并不能让我的客户满意。我想知道如果从M10到4未经许可的模式中缺少功能个XenApp VM配置4个GPU的直通，哪些功能将会丢失。据我在屏幕截图中看到，有一个名为“Tesla unlicensed”的许可模式。该模式有哪些限制？我只需要Office＆amp; amp;的图形加速在具有2个FHD显示器的瘦客户机上运行的Web浏览器......感谢您的回复！以上来自于谷歌翻译以下为原文Currently for one of my customers I'm writing a design for new hardware for new XenApp hosts. One of the requirements is an GPU for graphics acceleration. All XenApp users are task-/knowledge workers.I'm a great fan of the GRID solutions but the additional costs for the licensing component in GRID 2.0/3.0doesn't make my customer happy. I'm wondering which features will be missing if configuring a passthrough of the 4 GPUs from a M10 to 4 XenApp VM's. As far as I saw in screenshots there's a license mode named 'Tesla unlicensed'.What are the restrictions of that mode?I only need graphics acceleration for Office & web browsers running on a thin client with 2 FHD displays... Thanks for your reply!
2018-09-06 10:09
