ICD4网页表明，相关的外部电源工具是AC2014。DigiKy和MuleR都表示该部件的直流插头为2.1mm的ID×5.5mm OD。我买了一个同样规格的电源，但插头不适合ICD4。我刚刚在Microchip直接找到，AC2014是一个替代的FACAC202039。在DigiKEY上的ANAC162039是2.5mm的ID。您是否能够确认AC2014是ICD4的正确电源，如果是的话，DC插头的尺寸是多少？ 以上来自于百度翻译 以下为原文 The ICD4 webpage indicates that the related tool for external power is AC002014. Both digikey and mouser indicate that the DC plug for this part is 2.1mm ID x 5.5mm OD. I bought a similar power supply with the same specs but the plug does not fit into the ICD4. I just found on Microchip Direct that the AC002014 is a replacement for AC162039. And AC162039 on digikey is 2.5mm ID... Would you be able to confirm that the AC002014 is the correct power supply for the ICD4 and, if so, what the dimensions of the DC plug is?
2018-11-05 14:57
嗨，我使用virtex7 xc7vx690t来运行P＆amp; R但总是得到unrouted网络的错误。但我发现报道的错误是“BUFG驱动SLICE”。我认为BUFG是全球时钟资源，它可以驱动FPGA中的任何逻辑。对？那为什么报告错误？Post Initial-Routing Verification --------------------------------- CRITICAL WARNING：[Route 35-54] Net：U_clock_gen / rclk未完全路由。解决方案：运行report_route_status以获取更多信息。紧急警告：[Route 35-54] Net：U_u_iip_wrapper / U_3 / U_3_clk / U_3_clk_mux_dft_mac2_clk / mac_clk未完全路由。解决方案：运行report_route_status以获取更多信息。Unroutable connection类型：----------------------------类型1：BUFGCTRL.O-> SLICEM.CLK ----- Num Open网：67 -----代表网：网[35] U_clock_gen / rclk ----- BUFGCTRL_X0Y20.O- > SLICE_X146Y250.CLK -----驱动程序术语：U_clock_gen / U_rclk / O加载项[15481]： U_clock_gen / U_3_sync_ctl_powerdown / async_inst.U_bcm41_w_async_rst / U_SYNC / GEN_FST2.U_SAMPLE_META_2 [1] / sample_meta / CType 2：BUFGCTRL.O-> SLICEL.CLK ----- Num Open nets：57 -----代表网：净[ 35] U_clock_gen / rclk ----- BUFGCTRL_X0Y20.O- > SLICE_X123Y250.CLK -----驱动程序术语：U_clock_gen / U_rclk / O加载项[15480]：U_clock_gen / U_3_sync_ctl_powerdown / async_inst.U_bcm41_w_async_rst / U_SYNC / GEN_FST2.U_SAMPLE_META_2 [0] / sample_meta / C以上来自于谷歌翻译以下为原文Hi ,I use virtex7 xc7vx690t to run a P&R but always got the error of unrouted nets.But I found the reported error was saying " BUFGdrives SLICE". I think BUFG is global clock resource and it can drive any logic in the FPGA. Right? Then why it reported the error? Post Initial-Routing Verification---------------------------------CRITICAL WARNING: [Route 35-54] Net: U_clock_gen/rclk is not completely routed.Resolution: Run report_route_status for more information.CRITICAL WARNING: [Route 35-54] Net: U_u_iip_wrapper/U_3/U_3_clk/U_3_clk_mux_dft_mac2_clk/mac_clk is not completely routed.Resolution: Run report_route_status for more information.Unroutable connection Types:----------------------------Type 1 : BUFGCTRL.O->SLICEM.CLK-----Num Open nets: 67-----Representative Net: Net[35] U_clock_gen/rclk-----BUFGCTRL_X0Y20.O -> SLICE_X146Y250.CLK-----Driver Term: U_clock_gen/U_rclk/O Load Term [15481]: U_clock_gen/U_3_sync_ctl_powerdown/async_inst.U_bcm41_w_async_rst/U_SYNC/GEN_FST2.U_SAMPLE_META_2[1]/sample_meta/CType 2 : BUFGCTRL.O->SLICEL.CLK-----Num Open nets: 57-----Representative Net: Net[35] U_clock_gen/rclk-----BUFGCTRL_X0Y20.O -> SLICE_X123Y250.CLK-----Driver Term: U_clock_gen/U_rclk/O Load Term [15480]: U_clock_gen/U_3_sync_ctl_powerdown/async_inst.U_bcm41_w_async_rst/U_SYNC/GEN_FST2.U_SAMPLE_META_2[0]/sample_meta/C
2018-11-13 14:16
虽然格林斯潘称危机已经触底，但对产业而言，危机带来的影响或正渗透。对于半导体业而言，灵活的高性能、低成本解决方案无疑更具优势。因此，有人预言，因为FPGA特有的可编程特性与较之以往的成本优势，其黄金时代正式到来。与此同时，无可辩驳的，中国半导体产业的一大遗憾是我们几乎没有自己的核心芯片，无论MCU、DSP或是FPGA等，主流技术仍被国际厂商所垄断。
2019-11-01 08:12
大家好，我很乐意听到关于“不关心”作为重置值的意见：我的设计很大，很难满足时机要求。我的大多数模块都被编码为单个同步过程;那里的重置是同步的。对于我设计中的许多寄存器，复位值不是必须的，因为，例如，它们中的许多只是一些流水线寄存器，伴随着一些“有效”位（“有效”位确实有复位值）。我几乎在任何模块中使用本地同步复位。目前的情况是，在整个设计过程中，每个模块中的复位逻辑都有很大的扇出，进入该模块中的每个寄存器。我在某些地方看到Xilinx建议尽可能避免复位逻辑，以减少布线资源并帮助满足时序要求。我没有看到的是建议如何做到这一点。我假设最简单的方法是使用多个进程编写Verilog / VHDL代码，其中一些进程没有重置逻辑。如上所述，我的项目每个模块只有一个同步过程。我看到如果我只是不为某个寄存器写入任何复位值，那么该寄存器仍然有复位扇出和逻辑，因为对于该寄存器，ISE使逻辑在复位期间“保持”该值;因此，复位然后与那些触发器的“使能”端口相关，或者，ISE从触发器输出到其输入端产生多路复用器，以便在复位周期期间保持值。我想删除所有寄存器的复位逻辑，其中不必具有复位值，以减少布线资源并帮助满足时序要求。我打算写一个“不关心”的值作为所有那些寄存器的复位分配，这些寄存器不必具有复位值。我对此做了一些实验，并在RTL和技术观察者看到它似乎成功了：假设我们正在谈论一些流水线寄存器：在这种情况下，如果它有一个“不关心”作为其复位值，我看到ISE然后完全忽略（如预期）复位输入，并且只保留主逻辑该登记册。因此，似乎这种“不关心”的方法确实有助于减少重置扇出（从而减少路由资源并有助于满足时序）。我知道“不关心”值可能导致模拟和硬件在复位期间的不同行为，但这对我的情况来说是好的。我只是想知道在这样做时我是否还有其他缺点？我很乐意听到这方面的意见。谢谢 ：-）欧文以上来自于谷歌翻译以下为原文Hello everybody, I would be happy to hear opinions regarding "don’t care" as reset value: I have a large design, which is hard to meet timing.Most of my modules are coded as a single synchronous process; The reset there is synchronous. For many of the registers in my design, a reset value is not a must, since, for example, many of them are just some pipeline registers, accompanied by some "valid" bit (the "Valid" bits do have reset values).I use local synchronized reset in almost any module I have. The current situation is that throughout the design, the reset logic in each module has large fanout, going to each and every register in that module. I saw in some places Xilinx recommendations to avoid reset logic, whenever possible, in order to reduce routing resources and help meet timing.What I did not see, is a recommendation how to do it.I assume that the easiest way is to write the Verilog / VHDL code with multiple processes, where some of them would not have reset logic. As mentioned, my project has a single synchronous process per module.I saw that if I simply do not write any reset value for some register, there still is reset fanout and logic to this register, since for this register, the ISE makes logic to "keep" the value during reset;Hence, the reset then is either related to the "enable" port of those flip-flops, or, ISE makes a mux from the flip-flop output to its input, in order to maintain value during reset period. I would like to remove reset logic for all registers where it is not a must to have a reset value, in order to reduce routing resources and help meet timing. I intend to write a "don't care" value as reset assignment for all those registers which is not a must to have reset value for them.I made some experiment on this, and saw in the RTL and technology viewers that it seems like it makes the job:Say we are talking about some pipeline register: in that case, if it has a "don't care" as its reset value, I saw that the ISE then completely ignores (as expected) the reset input, and only keep the main logic for that register. Hence, seems like this "don't care" approach indeed help reduce reset fanout (and thus reduce routing resources and also help meet timing). I am aware that a "don’t care" value might lead to different behavior in simulation and on hardware for the reset period, but this is ok for my case. I just wonder if there is some other disadvantage that I might miss here in doing so? I would be happy to hear opinions on this. Thank you :-) Owen
2019-03-18 13:53
CS5484具有什么特性？CDB5484U评估板主要特性Cirrus CS5484高精度四路能量测量模拟前端解决方案
2021-04-20 06:53
