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  • 如何设计两个连续的PLL

    你好我想用PLL来产生一个基本时钟,而我想用第二个PLL来驱动它。请求的背景是我有一个输入时钟为26 MHz的Spartan 6。我想从26 MHz产生一个120 MHz和30MHz的时钟。然而,斯巴达6未能实现这一目标。这就是我使用第一个PLL产生30MHz时钟的原因。我使用30 MHz时钟作为另一个具有30 MHz和120 MHz输出的PLL的输入。我已经实现了如上所述的这种设计,但我遇到了稳定性问题。有关于这种设计的设计参考吗?亲切的问候,Kornad以上来自于谷歌翻译以下为原文Hi I'd like to use a PLL to generate a base clock, which in turn I would like to drive a second PLL with. The background to my request ist that I have a Spartan 6 with a input clock of 26 MHz. I'd like to generate a 120 MHz and 30MHz clock from the 26 MHz. However the Spartan 6 fails to achieve this goal. That is why I used a first PLL to generate a 30MHz clock. I used the 30 MHz clock as input to another PLL that has a 30 MHz and 120 MHz output. I have implemented such a design as described above, but I have run into stability problems. Are there any design references regarding such a design ? Kind Regards, Kornad

    2019-07-15 07:29

  • 有没有人成功创建过使用VSC8541以太网PHY的设计?

    有没有人成功创建过使用VSC8541以太网PHY的设计?我可以配置他们的芯片,看起来它试图自动协商链接(将逻辑分析仪放在RJ45终端上,这将是预磁性)。这是一个相当新的套件,所以我开始怀疑磁性是否配置不正确,我也没有发现任何人已成功完成VSC8541设计的任何迹象。我将套件连接到10/100/1000以太网交换机。这两种产品都支持自动MDIX检测,并且正在使用cat5e电缆。我也试过禁用自动协商并使用强制100Mbps而没有运气。汤姆以上来自于谷歌翻译以下为原文Has anyone successfully created a design that uses the VSC8541 Ethernet PHY? I can can configure they chip and it looks like its attempting to auto negotiate the link (put a logic analyzer on the RJ45 terminals that would be pre-magnetics). This is a fairly new kit so I am beginning to wonder if the magnetics are configured incorrectly, I also haven’t found any indication that anyone has successfully completed a design with the VSC8541.I have the kit connected to a 10/100/1000 Ethernet switch. Both products support auto MDIX detection and cat5e cables are being used. I have also tried disabling auto negotiation and using forced 100Mbps with no luck.Tom

    2018-10-23 11:32