RGMII_rxc]异步输入的#false路径约束直接来到synchronizerset_false_path -to [get_pins -hier -filter {name
2020-08-26 09:39
到u_ddr_mc_phy，我用完整的层次结构实例名称描述了它。set_property LOC OUT_FIFO_X1Y34 [get_cells -hier -filter {NAME
2018-10-19 14:31
'ap_reg_ppstg_col_assign_reg_607_pp0_it4_reg'，并将其从'32'修剪为'11'位。 ]我在Tcl控制台中使用以下命令来解决此问题。connect_net [-hier
2020-04-16 08:15
LOC GTHE3_COMMON_X0Y8 [get_cells -hier -filter {NAME =〜ten_gig_eth_pcs_pma_core_support_layer_i
2020-05-20 08:03
和hier是正确的，所以我猜Vivado对工作顶级模块是什么感到困惑？ （尽管在我合成时会突出显示正确的顶级模块）。以上来自于谷歌翻译以下为原文I have a relatively simply
2018-11-05 11:32
亲爱的先生，我正在使用synplify D-2010.03，ISE 13.1（lin 64）和Spartan 6 XC6SLX150 FGG676为我在SDI的项目进行FPGA测试应用。我正在使用的流程是合成verilog代码，其中包含从coregen生成的一些DCM一个约束文件，top.sdc，在Synplify上，到geta网表。然后我使用输出网表文件.edf和.ucf文件来生成ISE的编程文件或仿真模型。我在FPGA板上看到的测试结果似乎与后标准不同模拟。为什么？约束是否与电路板条件不匹配？或者，导致不匹配的任何其他原因？谢谢。另一个问题是如何在我正在运行的情况下保持设计层次结构？在UCF中KEEP_HIERARCHY？它似乎不起作用。谢谢。彼得昌以上来自于谷歌翻译以下为原文Dear Sir, I'm using synplify D-2010.03, ISE 13.1(lin 64) and Spartan 6 XC6SLX150 FGG676 to do a FPGA test for my project in SDIapplication.The flow I'm using is synthesize the verilog codes which contains some DCM generated from coregen, witha constraint file, top.sdc, on the Synplify, to get a netlist.And then I use the output netlist file, .edf, with a .ucf file to generatea programing file or simulation model by ISE.The test result I saw on the FPGA board seems different from the post-parsimulation.Why?Does the constraints not match the board condition?Or, any other reasons to cause the mismatch?Thanks.Another question is about how to keep the design hierarchy in the case I'm running?KEEP_HIERARCHY in UCF?It seems doen't work.Thanks. Peter Chang
2019-07-24 08:23
;//Hier muss je nach verwendetem Handle ausgelesen werdenrsp.attr_value.value[0] = 0x16
2023-04-13 08:04
嗨，我有一个使用LUTx原语设计的exorgate。一些LUT具有标签，例如xorgate32.vhd文件中的标签“xorgate32_TLUT1_a134not”（附件）。我已经打包了xorgate32.vhdas用户IP（称为axi_xor_2016）。该IP安装在AXI总线上以连接Zynq PS。我试图使用TCL命令“get_cells”逐步读取设计层次结构，直到我到达axi_xorIP。我期待标签出现在列表中。我的主要目标是为xorgate的所有放置的LUT获取切片坐标。首先，我想在xorgate的层次结构级别读取所有放置的LUT的列表，然后获取每个LUT的name属性。请让我知道我该怎么做。谢谢。xorgate32.vhd 7 KB以上来自于谷歌翻译以下为原文Hi,I have an exor gate designed using LUTx primitive. Some LUTs have labels for example, the label "xorgate32_TLUT1_a134not" in the xorgate32.vhd file (attached). I have packed the xorgate32.vhd as user IP (called axi_xor_2016). This IP is mounted on AXI bus to connect the Zynq PS.I am trying to use TCL command "get_cells" to read the design hierarchy step by step until I reach the axi_xor IP. I was expecting the labels to appear on the list. My main objective is to get the slice coordinates for all placed LUTs of the xorgate. For this first, I want to read a list of all placed LUTs at the level of the hierarchy of xorgate, and then get the name property for each one. Please let me know how can I do this. Thanks.xorgate32.vhd 7 KB
2018-11-13 14:28
。这种设计以及多种配置在电路中工作。为什么会这样？我使用get_pplocs -pin [get_pins -hier *]获取分区引脚信息。2.似乎如果我决定更新静态区域的rtl（而不是接口引脚）并重
2018-11-12 14:45
怎样去设计一种基于STM32F429-Discovery-Board的示波器呢？其代码该如何去实现呢？
2021-11-18 07:48
