AD17 跟踪修线是如何操作的？跟踪修线菜单在哪里？
2019-05-30 05:35
or just gloss over it with little explanation. The DMA Wizard doesn't support USB. Any suggestions on where else to look? Thanks
2019-01-17 13:07
嗨，大家好，我们都知道系统genreator可以生成硬件语言（verliog和VHDL）。但我的问题是：与专业的HDL程序员相比，如何更好地了解系统生成器生成的这些代码，哪一个更有效？问候瑞安以上来自于谷歌翻译以下为原文Hi everyone, we all knows system genreator could generate hardware languages (verliog and VHDL). But my question is that: Compare to professional HDL programmers,how good about these codes generated by system generator, which one is moreefficency? Regards Ryan
2019-02-20 10:25
我对编程的mcu风格比较熟悉，所以我在这里使用术语“中断”。我有一个模块，它打算读取FPGA外部引脚的频率。该模块具有16个外部上升沿的ref计数，并在50Mhz的ref时钟内部计数。在16时钟，它将值锁存到寄存器中。现在如果我在顶层实例化这个模块，我想知道如何知道新计数何时被锁存？我的模块看起来像这样模块捕获（输入ref_clk，// 50 MHz refinput in_clk，// freq to countinput reset，output reg [23：0] f_meas）;我想知道我是否可以从该模块中“准备好”了？但是我需要在我的顶级模块中做这样的事情总是@（posedge ready）开始//在此处理f_meas值结束有没有优雅的方法来做到这一点。简而言之，我只想在uart上准备好一个新值时立即发送“f_meas”。以上来自于谷歌翻译以下为原文I'm more familiar with the mcu style of programming so I use the term interrupt here. I have a module that intends to read a frequency on an external pin of the FPGA. The module has a ref counts 16 external rising edges and counts internal at a ref clock of 50Mhz. At the 16 clock it latches the value into a register. Now if I instantiate this module in my Top level, I was wondering how do I know when a new count as been latched? My module looks like this module capture(input ref_clk, // 50 MHz refinput in_clk, // freq to be countedinput reset,output reg [23:0] f_meas ); I was wondering if I could give a "ready" out from that module? but then would I need to do something like this in my top level module always @ (posedge ready) begin // process the f_meas value hereend Are there any elegant ways of doing this. In short i just want to send"f_meas" as soon as a new value is ready on the uart to the pc.
2019-06-17 08:13
