电子发烧友

#define CCxxx0_IOCFG2 0x00// GDO2 output pin configuration#define CCxxx0_IOCFG1 0x01// GDO1 output pin configuration#define CCxxx0_IOCFG0 0x02// GDO0 output pin configuration#define CCxxx0_FIFOTHR0x03// RX FIFO and TX FIFO thresholds#define CCxxx0_SYNC10x04// Sync word, high INT8U#define CCxxx0_SYNC00x05// Sync word, low INT8U#define CCxxx0_PKTLEN 0x06// Packet length#define CCxxx0_PKTCTRL10x07// Packet automation control#define CCxxx0_PKTCTRL00x08// Packet automation control#define CCxxx0_ADDR0x09// Device address#define CCxxx0_CHANNR 0x0A// Channel number#define CCxxx0_FSCTRL10x0B// Frequency synthesizer control#define CCxxx0_FSCTRL00x0C// Frequency synthesizer control#define CCxxx0_FREQ20x0D// Frequency control word, high INT8U#define CCxxx0_FREQ10x0E// Frequency control word, middle INT8U#define CCxxx0_FREQ00x0F// Frequency control word, low INT8U#define CCxxx0_MDMCFG40x10// Modem configuration#define CCxxx0_MDMCFG30x11// Modem configuration#define CCxxx0_MDMCFG20x12// Modem configuration#define CCxxx0_MDMCFG10x13// Modem configuration#define CCxxx0_MDMCFG00x14// Modem configuration#define CCxxx0_DEVIATN0x15// Modem deviation setting#define CCxxx0_MCSM20x16// Main Radio Control State Machine configuration#define CCxxx0_MCSM10x17// Main Radio Control State Machine configuration#define CCxxx0_MCSM00x18// Main Radio Control State Machine configuration#define CCxxx0_FOCCFG 0x19// Frequency Offset Compensation configuration#define CCxxx0_BSCFG0x1A// Bit Synchronization configuration#define CCxxx0_AGCCTRL20x1B// AGC control#define CCxxx0_AGCCTRL10x1C// AGC control#define CCxxx0_AGCCTRL00x1D// AGC control#define CCxxx0_WOREVT10x1E// High INT8U Event 0 timeout#define CCxxx0_WOREVT00x1F// Low INT8U Event 0 timeout#define CCxxx0_WORCTRL0x20// Wake On Radio control#define CCxxx0_FREND1 0x21// Front end RX configuration#define CCxxx0_FREND0 0x22// Front end TX configuration#define CCxxx0_FSCAL3 0x23// Frequency synthesizer calibration#define CCxxx0_FSCAL2 0x24// Frequency synthesizer calibration#define CCxxx0_FSCAL1 0x25// Frequency synthesizer calibration#define CCxxx0_FSCAL0 0x26// Frequency synthesizer calibration#define CCxxx0_RCCTRL10x27// RC oscillator configuration#define CCxxx0_RCCTRL00x28// RC oscillator configuration#define CCxxx0_FSTEST 0x29// Frequency synthesizer calibration control#define CCxxx0_PTEST0x2A// Production test#define CCxxx0_AGCTEST0x2B// AGC test#define CCxxx0_TEST20x2C// Various test settings#define CCxxx0_TEST10x2D// Various test settings#define CCxxx0_TEST00x2E// Various test settings// Strobe commands#define CCxxx0_SRES0x30// Reset chip.#define CCxxx0_SFSTXON0x31// Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). // If in RX/TX: Go to a wait state where only the synthesizer is // running (for quick RX / TX turnaround).#define CCxxx0_SXOFF0x32// Turn off crystal oscillator.#define CCxxx0_SCAL0x33// Calibrate frequency synthesizer and turn it off // (enables quick start).#define CCxxx0_SRX 0x34// Enable RX. Perform calibration first if coming from IDLE and // MCSM0.FS_AUTOCAL=1.#define CCxxx0_STX 0x35// In IDLE state: Enable TX. Perform calibration first if // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: // Only go to TX if channel is clear.#define CCxxx0_SIDLE0x36// Exit RX / TX, turn off frequency synthesizer and exit // Wake-On-Radio mode if applicable.#define CCxxx0_SAFC0x37// Perform AFC adjustment of the frequency synthesizer#define CCxxx0_SWOR0x38// Start automatic RX polling sequence (Wake-on-Radio)#define CCxxx0_SPWD0x39// Enter power down mode when CSn goes high.#define CCxxx0_SFRX0x3A// Flush the RX FIFO buffer.#define CCxxx0_SFTX0x3B// Flush the TX FIFO buffer.#define CCxxx0_SWORRST0x3C// Reset real time clock.#define CCxxx0_SNOP0x3D// No operation. May be used to pad strobe commands to two // INT8Us for simpler software.#define CCxxx0_PARTNUM0x30#define CCxxx0_VERSION0x31#define CCxxx0_FREQEST0x32#define CCxxx0_LQI 0x33#define CCxxx0_RSSI0x34#define CCxxx0_MARCSTATE 0x35#define CCxxx0_WORTIME10x36#define CCxxx0_WORTIME00x37#define CCxxx0_PKTSTATUS 0x38#define CCxxx0_VCO_VC_DAC0x39#define CCxxx0_TXBYTES0x3A#define CCxxx0_RXBYTES0x3B#define CCxxx0_PATABLE0x3E#define CCxxx0_TXFIFO 0x3F#define CCxxx0_RXFIFO 0x3F

2015-08-28 11:18