now.I am about to try and just create a quick machine with a k2 card and slap on the current driver
2018-09-07 16:47
自从一个多月以来，我总是得到“小窗口”没有菜单栏和舒适的大小。我已经跟踪到这是我的Internet Explorer IE10的一个设置，实际版本。我创建了一个MyCase.当没有回应的时候，我把它升级了。塞浦路斯的最后一个回应是一个月的承诺。在我的实验室里有几台机器能正确显示后窗，这两台机器的比较没有显示出明显的差别。取消和重新安装IE10并不能治愈这个错误。这是不可能的，我在这个机器上使用一个不同的浏览器比IE，因为一些安全限制，我已经签署并必须遵循。欢迎您的任何建议！鲍伯（绝望的）附图显示了我的“小窗口”错误。JPG66.7 K 以上来自于百度翻译 以下为原文 Since more than a month now I *always* get the "small window" without the menu-bar and comfortable size. I tracked down already this to be a setting of my internet-explorer ie10, actual version. I created a MyCase and when no response came I escalated it. Last response from Cypress now is one month old promising nothing. In my lab are a few machines that show the post-window correctly, the comparision of the two machines did not reveal a visible difference. De- and reinstallation of ie10 did not cure the error. It is not possible for me to use on this machine a different browser than ie due to some security restrictions I have signed and have to follow. Any suggestions from your side are welcome! Bob (desperated) Attached picture shows my "small Window" error. post.jpg 66.7 K
2019-06-26 07:18
您好，我已经能够在RAM中指定一个特定地址的RAM，但我的问题是，是否有一种简单的方法使用地址而不是变量名从RAM位置提取数据呢？我是一个编程新手，我似乎找不到一个简单的方法来获取这些信息。非常感谢，吉姆。 以上来自于百度翻译 以下为原文 Hello, I have been able to assign some ram at a specific address in ram but my question is, is there a simple way to extract the data from the ram location using the address rather than the variable name?I am somewhat of a newbie to programming and I can not seem to find an easy way to get this information. Much Thanks,Jim
2018-12-17 16:46
这是我的代码：非常简单。我的代码字，但文件寄存器Windows DIFF0永远不会更新？其他人都这么做。我也尝试添加一个手表的IDF0，它是AlrFead 0，但我的PROFAM工作如预期。我确实检查了项目设置中的框，“内置的绝对模式”。任何帮助都会得到极大的赞赏。产品版本：MPLAB X IDE V3.50Java:1.8 091；Java热点（TM）64位服务器VM 25.91-B14RunTime:Java（TM）SE运行时环境1.80Y91-B14Stase:Windows 7版本6.1在AMD64上运行。CP1252；EN（MPLAB） 以上来自于百度翻译 以下为原文 Here is my code: radix HEX list p=16f1827#include "p16f1827.inc" org 000 movlw 26 movwf FSR0START movwf INDF0 movf FSR0,INDF0 incf FSR0,1 goto START END Quite simple.My code words, but the File Register window INDF0 never updates?? All the others do. I also tried to add a watch for INDF0, it is allway 0, but my progam works as expected.I did check the box in the project settings, "Build in absolute mode". Any help would be greatly appreciated. Product Version: MPLAB X IDE v3.50Java: 1.8.0_91; Java HotSpot(TM) 64-Bit Server VM 25.91-b14Runtime: Java(TM) SE Runtime Environment 1.8.0_91-b14System: Windows 7 version 6.1 running on amd64; Cp1252; en (mplab)
2019-03-26 11:25
原谅我的无知，但我是一个来自软件背景的FPGA的n00b。就像这张表上5000张其他n00b海报一样，我想使用我的spartan-3e的以太网功能。没有人在网上实际上有一个现成的复制/粘贴解决方案，这对我来说没问题。我会做的工作并弄清楚。我已经完成了很多功课，但总的来说我对一件事感到困惑......我知道有两种基本的方法可以使用以太网控制器：使用xilinx IDE提供的免费IP核，或者自己编写VHDL / verilog并正确地敲出MII接口。后一种方法显然是一种皇家的痛苦，因为你必须计算校验和，否则操纵TCP / UDP数据包的可能性最低......我的问题是：我的应用程序要求以尽可能低的开销来处理数据包。如果我不需要，我甚至不想等待一个额外的时钟周期。我的理解是，你放在FPGA上的任何*核心*实际上都是一个“软核”处理器，换句话说，存在来自这些不同IP核的强大功能，因为FPGA是用VHDL指令编程的，模拟比如说一个8086 CPU基本上运行用C或程序集编写的虚拟8086程序，因为使用这些语言要比VHDL容易得多。那是对的吗 ？如果是这样，这是否意味着我希望我的整体网络性能比我自己直接写入处理的速度慢？如果没有，那么“核心”可以与直接VHDL程序共存，就像我链接到C中的外部符号一样吗？或核心消耗整个芯片？感谢您抽出宝贵时间回复n00b。我很感激。-n00b以上来自于谷歌翻译以下为原文forgive my ignorance but I'm a n00b to FPGA coming from a software background. Just like 5000 other n00b posters on this form, I want to use the ethernet capabilities of my spartan-3e. Nobody online actually has a ready-made copy/paste solution for this, and that's ok by me. I'll do the work and figure it out. I've already done a lot of the homework, but I'm confused about one thing in general... I'm aware that there are two fundamental ways to use the ethernet controller: using the free IP core that xilinx's IDE offers, or writing VHDL/verilog myself and correctly banging out an MII interface. The latter method is a royal pain apparently because you have to calculate checksums and otherwise manipulate TCP/UDP packets at about the lowest level possible... My question is this: My application requirespackets to be processed with the lowest amount of overhead possible. I don't even want to have to wait one extra clock cycle if I don't have to. My understand was that any *core* that you put on an FPGA is effectively a "soft-core" processor, in other words, the robust functionality from these various IP cores exists because the FPGA is programmed with VHDL instructions that simulate, say, an 8086 CPUthat basically run a program written in C or assembly for this virtual 8086, since it's a lot easier to use these languages than VHDL. Is that correct ? If so, does that mean I would expect my overall network performance to be slower than if I wrote the processing myself in straight-vhdl ? If not, then can a "core" coexist with a straight VHDL program, the same way as I would link to an external symbol in C ? Or does the core consume the whole chip ? Thank you for taking the time to respond to a n00b. I appreciate it. -n00b
2019-05-31 03:31
