Connect style ,点中Polygon Connect style，右键点击new rule ---------------新建一个规则，点击新建的规则既选中该规则，在name框中改变里面的内容
2011-03-23 10:03
on Designer5.4CommonCypressSemiBuildMgrtoolsincludeCY8C21030 - 3 make: *** No rule to make target `E:Program\', needed by `lib/obj/csd.o\'. Stop.
2024-01-26 07:29
make: *** No rule to make target 'all'.Stop.
2018-12-17 11:18
1.问题如下： rtthread出现 make: *** No rule to make target \'lv_port_disp.o\', needed by \'rtthread.elf
2024-03-22 08:18
Altium designer PCB 在使用PCB filter时候出现 expression expected but is found at line2,char46.这个问题该怎么解决呢？百度上说是rule设
2017-11-05 22:47
Protel PCB默认导线宽度在哪里设置？ 找了很久，不知是我软件问题还是什么，不是RULE里面设置吗
2010-08-27 15:53
本帖最后由 gk320830 于 2015-3-4 16:37 编辑 我之前用的AltiumDesigner9绿色版的，然后删了绿色版又装了AD9安装版的，结果design rule
2014-11-12 12:26
)為確保產品之製造性, R&D在設計階段必須遵循Layout相關規範, 以利製造單位能順利生產, 確保產品良率, 降低因設計而重工之浪費. “PCB Layout Rule
2008-06-29 02:04
编译KeyStone1SelfTestKit中的例程的时候提示“gmake;***No rule to make target 'D:/DSPworkspace/common/common_test.c',needed by `src/common_test.obj`”怎么解决
2018-06-21 01:14
/DesignRule_RoutingWidthAddNew.png]The Routing Width design rule, which was configured by the PCB Board
2015-01-27 10:24
