你好，我尝试使用GLCD控制器组件与480X222 8位CO.，触摸屏，PSoC5-60MHz。它可以是非常有用的组件，但绘制显示是相当缓慢的。是的，我可以使用虚拟页面，但是它花费了大量昂贵的SRAM（帧缓冲区）。我在GLCD控制器数据表中发现写入帧缓冲区在消隐间隔中继续进行。尝试大家用自己的组件来写两帧之间的帧缓冲为目的加速？（控制寄存器+多路复用器或Verilog组件）？最终有什么办法可以提高速度吗？谢谢，简 以上来自于百度翻译 以下为原文Hi, I tried to use GLCD controller component with 480x272 8bit col., touchscreen, PSOC5-60MHz.It could be very usefull componet, but drawing to displayis quite slow. Yes, i could use virtual page, but it spend large amout of expensive SRAM(frame buffer). I find out in GLCD controller datasheet that writing to frame buffer proceed on in blanking intervals.Try everyone to write to frame buffer between two posedge dotclock using own component for the purpose acceleration? (controll registers+mux or verilog componet)? Eventually any idea to improve draving speed? Thanks, Jan
2019-06-06 15:13
您好!最近，我通过电子邮件询问CyPress客户关怀，以了解CyPress是否支持新的创新来启动创业。以下是我的邮件：“我是Alireza Alikhani，我是一名设计师和一名电子工程师。在接下来的几天里，我将展示我的两个设计/发明，这些都是基于CyPress技术（PSoC4BLE和CAPSENSE）。我对我的设计和想法充满信心，我相信这可以启动一个成功的创业。我想知道，如果塞浦路斯有任何程序支持和支持选定的设计，并帮助他们介绍自己？我非常渴望与柏树合作，因为他们为我提供了一个坚实的平台和设计套装，这对我很好地实现了我的想法。但他们建议我发表一个新的话题，我认为这只是一个自动回答。不管怎样，我想知道塞浦路斯是否支持我们，帮助我们展示我们的创新。贝茨 以上来自于百度翻译 以下为原文Hi Recently I asked cypress customer care via its email to know that if Cypress supports new innovations to launch an startup. The following is my mail:" I’m Alireza Alikhani and I’m a designer and an electronic engineer. In the coming days, I’m going to showcase two of my designs/inventions which are all based on Cypress technologies (PSOC4BLE and CAPSENSE). I’m confident with my designs and ideas which I believe can launch a successful startup. I want to know that if there exist any program supported by Cypress to qualify and support selected designs and help them to introduce themselves? I’m really eager to work with Cypress because they provided me a solid platform and design suits which helped me a lot to implement my ideas nicely. " But they referred me to post a new topic which i think was just an automatic answer. Anyway, I wanted to know if Cypress backs us and help us to showcase our innovations. Bests
2018-09-18 14:30
HI， 我正在设计FPGA开发套件。在那里我想添加Nand Flash。使用nand flash与spartan系列fpga的优点是什么。我需要支持文档.reference schematics.Please Help Me。以上来自于谷歌翻译以下为原文HI,I am designing FPGA development kit . In that i would like to add Nand Flash.what will be the advantage of using nand flash with spartan series fpga. I needsupporting document .reference schematics.Please Help Me.
2019-05-23 09:55
原谅我的无知，但我是一个来自软件背景的FPGA的n00b。就像这张表上5000张其他n00b海报一样，我想使用我的spartan-3e的以太网功能。没有人在网上实际上有一个现成的复制/粘贴解决方案，这对我来说没问题。我会做的工作并弄清楚。我已经完成了很多功课，但总的来说我对一件事感到困惑......我知道有两种基本的方法可以使用以太网控制器：使用xilinx IDE提供的免费IP核，或者自己编写VHDL / verilog并正确地敲出MII接口。后一种方法显然是一种皇家的痛苦，因为你必须计算校验和，否则操纵TCP / UDP数据包的可能性最低......我的问题是：我的应用程序要求以尽可能低的开销来处理数据包。如果我不需要，我甚至不想等待一个额外的时钟周期。我的理解是，你放在FPGA上的任何*核心*实际上都是一个“软核”处理器，换句话说，存在来自这些不同IP核的强大功能，因为FPGA是用VHDL指令编程的，模拟比如说一个8086 CPU基本上运行用C或程序集编写的虚拟8086程序，因为使用这些语言要比VHDL容易得多。那是对的吗 ？如果是这样，这是否意味着我希望我的整体网络性能比我自己直接写入处理的速度慢？如果没有，那么“核心”可以与直接VHDL程序共存，就像我链接到C中的外部符号一样吗？或核心消耗整个芯片？感谢您抽出宝贵时间回复n00b。我很感激。-n00b以上来自于谷歌翻译以下为原文forgive my ignorance but I'm a n00b to FPGA coming from a software background. Just like 5000 other n00b posters on this form, I want to use the ethernet capabilities of my spartan-3e. Nobody online actually has a ready-made copy/paste solution for this, and that's ok by me. I'll do the work and figure it out. I've already done a lot of the homework, but I'm confused about one thing in general... I'm aware that there are two fundamental ways to use the ethernet controller: using the free IP core that xilinx's IDE offers, or writing VHDL/verilog myself and correctly banging out an MII interface. The latter method is a royal pain apparently because you have to calculate checksums and otherwise manipulate TCP/UDP packets at about the lowest level possible... My question is this: My application requirespackets to be processed with the lowest amount of overhead possible. I don't even want to have to wait one extra clock cycle if I don't have to. My understand was that any *core* that you put on an FPGA is effectively a "soft-core" processor, in other words, the robust functionality from these various IP cores exists because the FPGA is programmed with VHDL instructions that simulate, say, an 8086 CPUthat basically run a program written in C or assembly for this virtual 8086, since it's a lot easier to use these languages than VHDL. Is that correct ? If so, does that mean I would expect my overall network performance to be slower than if I wrote the processing myself in straight-vhdl ? If not, then can a "core" coexist with a straight VHDL program, the same way as I would link to an external symbol in C ? Or does the core consume the whole chip ? Thank you for taking the time to respond to a n00b. I appreciate it. -n00b
2019-05-31 03:31
