嗨，出于好奇我不知道是否有人会费心去回答这个问题，但是我第一次看到校准套件并且我的价格让我感到震惊。实际上从外面的材料看起来像钢连接器，泡沫，一个漂亮的木盒子。我只能想象，对于重复使用的公差，材料的等级有多精确，可能是高价来自或可能是因为它的独特性。可能他们是由我不知道的专家手工制作的。制造这种试剂盒需要什么样的特殊设备，内部是否有任何超昂贵的材料，安捷伦是否将它们作为第三方使用。 VNA是一种先进的电子机器，内部也必须具有精密机械部件，并且设计复杂，我觉得它们的价格不如校准套件高。另外我知道有些机器内部有一个工厂校准，如果它们没有标准可以召回，粗测量会有更多的不确定性。但是有可能在电缆末端使VNA完全自校准，也许可以使用VNA中自包含的标准。与现在的校准和验证套件和程序相比，这是否更实惠，更简单？顺便说一下，我喜欢木盒子，我希望安捷伦不要用塑料盒子来改变它们。 以上来自于谷歌翻译 以下为原文Hi, just out of curiosity I dont know if anyone would bother to answer this but the first time I looked at a calibration kit and the price at I was shocked. Actually from the outside the materials were a few look like steel connectors, foam, a nice wooden box. I can only imagine how precise has to be the tolerances, grade of materials for repeated use and probably that is where the high price comes from or maybe is because of its uniqueness. Probably they are hand made by experts I just dont know. What kind of special equipment is necessary to make this kits, is there any ultra expensive materials inside and does Agilent makes them o some third party.A VNA is a state of the art electronics machine that must have precision mechanical parts inside as well and with its design complexity I feel they are not as highly priced as cal kits.Also I know some machines have a factory cal inside that can be recalled in case they is no standards available, of coarse measurements will have more uncertainties. But would it be possible to make a VNA totally self calibrating at the end of the cables maybe with the standards self contained in the VNA. Could this be more affordable and less cumbersome than it is now with the calibration and verification kits and procedures? By the way I do love the wooden boxes I hope Agilent dont change them with plastic ones.
2019-02-28 15:00
大家好我有一些VHDL的经验。我的问题是，随着设计变得庞大和复杂，在实现的设计中引入了一些错误，我确信这是由于我的设计合成错误，而不是由我做出的逻辑/时间错误。我已经研究了很多关于这些错误的来源，并且我已经找到了一些预防它们的经验法则。例如，我知道单个vhd文件中不应该有多个状态机。但是，当我设计一个大型系统时，我不确定它的不同部分的正确功能。有时我会花几天时间尝试调试我的设计，最后我意识到设计本身没有错误，错误是错误合成的结果。例如，一个模块中的小而不重要的更改有时会使另一个完全独立的模块的操作停止。这太令人不安了。我想知道是否有一个全面的设计指南，其中包括必须遵守的所有细节，以达到正确合成的设计，其行为是完全可预测的。以上来自于谷歌翻译以下为原文Hello guysI have some experience with VHDL. My problem is that, as the design becomes large and complicated, some bugs are introduced into the implemented design, which I am certain that are due to bad synthesis of my design, and not logical/timing mistakes made by me. I have researched alot about the sources of such errors, and I have figured out some rules of thumb for preventing them. For example, I understand that there should not be more than one state machine in a single vhd file. But still, when I design a large system, I am not sure about correct functionality of it's different parts. sometimes it happens that I spend several days trying to debug my design, when at the end I realize that there is no error in the design itself, and the errors are the results of bad synthesis. For example, a small and unimportant change in one module, sometimes brings the operation of another, completely independant module to a halt. This is so troubling. I was wondering if there is a comprehensive design guidline, which includes all the details that must be observed in order to reach a correctly synthesized design whose behaviour is completely predictable.
2019-02-21 09:28
Mentors.187. 射频波段（MHz-GHz）电路板中的地连接问题 Please use one large complete consecutive groundplane and area.
2014-12-22 15:33
