This document describes and discusses the topic of CMOS Latch-Up ranging from theory to testing
2016-10-26 11:38
ESD/Latch-Up Considerations with iCoupler Isolation Products Analog Devices iCoupler products
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Latch-Up today is still a potentially potent source of failure in the qualification flow
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ADG5401:高伏特式Latch up,单片机SPST交换机
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USB Type-C应用中选错TVS造成的高度Latch-up风险
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IC工艺和版图设计第八章Latch-up和GuardRing设计
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摘要:闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试
2010-05-28 11:19
本帖最后由 不认识曹操 于 2011-12-16 17:07 编辑 [post][/post]Latch up 是指cmos晶片中, 在电源power VDD和地线GND(VSS)之间由于寄生
2011-12-16 16:37
静电放电/过度电性应力/闩锁试验 (ESD/EOS/Latch-up)EOS/ESD造成的客退情形不曾间断,IC过电压承受能力较低,产品就有损坏风险。 对成品厂商而言,除了要求IC供货商测试到所要
2018-09-18 09:09
to Parallel and Simple to Drive • Avalanche Ruggedness • Resistant to Latch-Up • Halogen Free, RoHS Compliant
2017-09-21 14:23