and/or PSoC5 ? Something which simulates the code and components? Hugo
2019-07-26 08:02
anywhere in the list of available components. I am using the CY8C3666LTI-027. Many thanks Hugo
2019-03-08 15:30
the SPI Master component, because I would like to make some slight modifications to the way it behaves. What's the easiest way to do this? Hugo
2019-04-28 13:23
cycles between the second and thirt bytes transmitted. How can I insert this delay using the hardware so that the CPU is not involved? Hugo
2019-05-07 14:47
A pure Verilog implementation makes less efficient use of the UDB, because it does not use the datapath? Hugo
2019-02-18 08:42
detects a finger, then the device would come into full wakefulness, and stay awake. Hugo
2019-04-16 16:33
be sent a development kit. The kit did not arrive, and now Amanda's e-mail address no longer works.Who at Cypress can I contact about this? Many thanks Hugo
2019-07-23 10:38
Is this possible? If so, is there a document explaining how to do this, and the format of the files I need to generate? Many thanks Hugo Elias
2019-07-09 08:25
Hello Hugo，如果协议有标头中的字节数（即数据包大小指示符），那么假设标题总是固定的字节数，那么首先要对标准数字进行二进制读取。头文件的字节然后解析并计算要读取多少字节，然后对该字节数进行
2018-09-05 09:50
the components in the project are using up about 9k of a total of 16k! Am I doing something wrong, or is the extra is coming from all the pins? Hugo Elias
2019-04-18 07:17
