如何去使用simulink-stateflow中的bus总线呢？bus总线有何作用呢？
2021-11-22 06:16
hat, I know, but it's an important legacy aerospace design, so no chance of using the latest stuff
2019-01-28 10:24
STM32系列在不久的将来是否会通过ISO26262（ASIL-B）认证？谢谢。以上来自于谷歌翻译以下为原文 Will the STM32 series be certified ISO26262 (ASIL-B) in the near future?Thanks.
2018-11-07 09:48
虽然北美国家大幅削减了国防工业的***预算，但目前该市场规模仍保持着约2.8％的复合年增长率（CAGR）。此外，估计商用航天航空业今后几年内将会大幅增长，因为金砖四国（BRICs）正纷纷推进飞机开发，法国空中客车（Airbus）和美国波音（Boeing）也都计划增产。
2020-05-04 07:48
你好，在文档“设备可靠性报告，2013”中，声明“在最坏的情况下，典型设计的设备漏洞因子（DVF）或SEUPI从不小于十分之一，或者从不超过10％的扰乱导致软功能错误“。我的问题是：在XQR4VSX55 CF1140 FPGA的情况下，这个％（10％最坏的情况）是否可以应用，是否有任何官方文档或科学研究证明这个因素，我可以作为参考？还指出“DVF由Xilinx ISE工具预测，以及非必要（未使用）位，工具还提供用户设计的预测平均软错误率”。我的问题是：可以使用什么工具来估算XQR4VSX55上的设计的DVF，以及如何估算软错误率。我知道带有-essentialbits的bitgen以及SEM IP内核可以做到这一点，但据我所知它们不能与virtex-4一起使用。有没有其他方法来估计virtex-4器件（XQR4VSX55）的基本位，以及我们如何计算同一器件的软错误率。谢谢克里斯泰勒以上来自于谷歌翻译以下为原文Hello, In the document "Device Reliability Report, 2013" it is stated that "In the worst case, the Device vulnerability factor (DVF) or SEUPI of a typical design is never smaller than one in ten, or never more than 10% of the upsets cause a soft functional error".My question is: Does this % (10% worst case) can be applied in the case of a XQR4VSX55 CF1140 FPGA, and is there any official documentation or scientific study where this factor is proved, that I can use as a reference ? It is also stated that "The DVF is predicted by the Xilinx ISE tools, along with the non-essential (unused) bits, The tools also provide the predicted average soft error rate for the user’s design".My question is: What tool can be used to get an estimate of the DVF for a design on XQR4VSX55, and how can the soft error rate be estimated.I know that bitgen with -essentialbits as well as the SEM IP core can do this but as far as I know they can't be used with a virtex-4. Is there any other way to estimate the essential bits of a virtex-4 device (XQR4VSX55) and how can we compute the soft error rate for this same device.Thank youChristelle
2019-02-26 10:24
, and edited a book on MEMS for aerospace and automotive applications. He currently serves on several steering
2015-09-25 10:22
求大神分享一些有关Matlab 2013a的全部官方帮助文档
2021-11-19 06:51
您好，转换加速度计和磁力计的输出与俯仰，滚转和偏航角度有关。我正在尝试使用DT0058的方程式。我写了下面的函数。void newPitchRollYaw（float * const acc，float * const mag） { float roll = atan2（acc [LSM303AGR_Y]，acc [LSM303AGR_Z] + acc [LSM303AGR_X] * 0.01）; float pitch = atan（-acc [LSM303AGR_X] /（acc [LSM303AGR_Y] * sin（roll）+ acc [LSM303AGR_Z] * cos（roll）））; float By2 = mag [LSM303AGR_Z] * sin（roll） - mag [LSM303AGR_Y ] * cos（roll）; float Bz2 = mag [LSM303AGR_Y] * sin（roll）+ mag [LSM303AGR_Z] * cos（roll）; float Bx3 = mag [LSM303AGR_X] * cos（pitch）+ Bz2 * sin（pitch）; float yaw = atan2（By2，Bx3）; float factor = LSM303AGR_180_DEGREES / LSM303AGR_PI; log_PushLine（e_logLevel_Info，'pitch：％f，roll：％f，yaw：％f'，pitch * factor，roll * factor，yaw * factor）;float Qw = cos（roll / 2）* cos（pitch / 2）* cos（roll / 2）+ sin（roll / 2）* sin（pitch / 2）* sin（roll / 2）; float Qx = sin（roll / 2）* cos（pitch / 2）* cos（roll / 2） - cos（roll / 2）* sin（pitch / 2）* sin（roll / 2）; float Qy = cos（roll / 2）* sin（pitch / 2）* cos（roll / 2）+ sin（roll / 2）* cos（pitch / 2）* sin（roll / 2）; float Qz = cos（roll / 2）* cos（pitch / 2）* sin（roll / 2） - sin（roll / 2）* sin（pitch / 2）* cos（roll / 2）; log_PushLine（e_logLevel_Info，' qw：％f，qx：％f，qy：％f，qz：％f'，Qw * factor，Qx * factor，Qy * factor，Qz * factor）;} 当罗盘围绕z轴旋转时，它会改变偏航值但非常不规则，例如从130到40然后形成-100到-30等。当我仅改变俯仰或滚转值时，偏航也会改变。我认为这不正确，因为设备的方向没有改变。例如，如果俯仰是1，则偏航是-50，如果俯仰是14偏航= -120。我不明白这些结果。我认为俯仰和滚动是正确的。 我在正常模式下使用加速度计，满量程默认值（+ - 2g），odr = 400 Hz，连续模式下的magetometer，100Hz。我不使用中断，只检查可用的数据。谢谢你的所有答案。以上来自于谷歌翻译以下为原文 Hello, I have a problem with conversion accelerometer's and magnetometer's output to pitch, roll and yaw angles. I am trying to use equations from DT0058. I wrote function like below.void newPitchRollYaw(float* const acc, float* const mag) { float roll = atan2(acc[LSM303AGR_Y], acc[LSM303AGR_Z] + acc[LSM303AGR_X] * 0.01); float pitch = atan(-acc[LSM303AGR_X] / (acc[LSM303AGR_Y] * sin(roll) + acc[LSM303AGR_Z] * cos(roll)));float By2 = mag[LSM303AGR_Z] * sin(roll) - mag[LSM303AGR_Y] * cos(roll); float Bz2 = mag[LSM303AGR_Y] * sin(roll) + mag[LSM303AGR_Z] * cos(roll); float Bx3 = mag[LSM303AGR_X] * cos(pitch) + Bz2 * sin(pitch);float yaw = atan2( By2 , Bx3); float factor = LSM303AGR_180_DEGREES / LSM303AGR_PI;log_PushLine(e_logLevel_Info, 'pitch: %f , roll: %f , yaw: %f', pitch * factor , roll * factor , yaw * factor);float Qw = cos(roll/2)*cos(pitch/2)*cos(roll/2) + sin(roll/2)*sin(pitch/2)*sin(roll/2); float Qx = sin(roll/2)*cos(pitch/2)*cos(roll/2) - cos(roll/2)*sin(pitch/2)*sin(roll/2); float Qy = cos(roll/2)*sin(pitch/2)*cos(roll/2) + sin(roll/2)*cos(pitch/2)*sin(roll/2); float Qz = cos(roll/2)*cos(pitch/2)*sin(roll/2) - sin(roll/2)*sin(pitch/2)*cos(roll/2);log_PushLine(e_logLevel_Info, 'qw: %f , qx: %f , qy: %f , qz: %f', Qw * factor, Qx * factor, Qy * factor, Qz * factor);}When compass rotates around z-axis it changes yaw value but very irregularly, for example from 130 to 40 and then form -100 to - 30 etc. When I change only pitch or roll value, yaw is also changed. I think that it's not correct, becausedevice's direction is no changed. For example if pitch is 1, yaw is -50, if pitch is 14 yaw = -120. I don't understand these results. I think that pitch and roll are correct. I use accelerometer in normal mode, full scale default ( +- 2g), odr = 400 Hz, magetometer in continuous mode, 100Hz. I don't use interrupts, only check data available.Thanks for all answers.
2018-10-15 11:02
大约6个月前，有人发布了PSoC 4设备中明显漏洞的全面解释。该漏洞将允许攻击者将恶意代码加载到Flash中，然后将其标记为保留给监控器，从而允许代码在芯片擦除中生存，并且几乎没有被检测到运行。正如他所解释的那样，这可能导致各种攻击向量，比如触摸屏设备的重放攻击。为乐趣和利润开发PSoC4——Dmitry Grinberg阅读不可读的SROM：在PSoC4 HKADADY内部据作者说，柏树还没有对此问题作出回应。那是6个月前的事了。柏树做了什么来减轻或消除这种脆弱性？这将严重减少适用于该芯片的应用范围，因此似乎不可能做任何事情。 以上来自于百度翻译 以下为原文About 6 months ago, someone posted a comprehensive explanation of an apparent vulnerability in PSoC 4 devices. The vulnerability would allow attackers to load malicious code to flash and then mark it as reserved for supervisor, allowing the code to survive chip erases and to run pretty much undetected. As he explains well, this potentially leads to all sorts of attack vectors, like replay attacks for touch screen devices. Exploiting PSoC4 for fun and profit - Dmitry Grinberg Reading the Unreadable SROM: Inside the PSoC4 | Hackaday According to the author, Cypress has not responded to the problem. That was 6 months ago. Has anything been done by Cypress to mitigate or remove this vulnerability? It would seriously reduce the range of suitable applications for this chip, so it seems unlikely nothing was done.
2019-01-09 13:58
我应该先说一下，我已经离开FPGA领域已经有几年了，并且对新一代的Xilinx硬件没有太多帮助。我来自一所设计理念的学校，它重视低级别的可访问性，清晰度和简单性，我一直在关注Xilinx工具的发展和迷恋。我早期的设计经验是使用Spartan-3和Virtex-IIProFPGAs。对我来说，这些芯片的吸引力在于ISE的设计流程以及完全按照我的意愿设计设计的能力，可以自由地实现实现和语法错误（并由ISE指出）。由于Xilinx已将设计师推向PlanAhead和Vivado，因此设计方向似乎朝着更高层次的方向发展，从设计师那里去除了设计控制的某些方面。图形架构，C到VHDL HLS，以及（据我所知，我可能是错误的）完全改进的后端消除了简单地编写脚本并修改基于文本的配置文件的能力。我注意到ISE已进入其生命的“持续”阶段。这意味着，在未来的某个时刻，ISE的过时将成为一个真正的关注点，以及为其支持的硬件构建的能力。 ISE的最终消亡不仅是一个问题，而且能够获得廉价，简单，裸露的FPGA，只需很少的花哨，如Spartan-6，可以用简单的文本编辑器编写，似乎也在养育它的头。所以我想我的问题就是这些。 ISE需要支持多长时间？ Spartan-6可以使用多长时间？有没有计划维护一系列简单的，精简的FPGA？ Vivado中是否有（或现在有）选项可以恢复到像Project Navigator这样的低级HDL / UCF设计流程用于裸逻辑设计？或者Vivado会继续将设计流程从HDL架构转移到高级功能块生成器吗？谢谢你的时间。以上来自于谷歌翻译以下为原文I should preface this by saying that I've been out of the FPGA field for a couple of years now, and haven't worked much with newer generations of Xilinx hardware. I come from a school of design philosophy that values low-level accessibility, clarity, and simplicity, and I've been watching the progression of Xilinx tools with fascination and a small measure of concern. My early design experiences were with Spartan-3 and Virtex-II Pro FPGAs. For me, the appeal of those chips was the design flow of ISE and the ability to architect a design exactly as I wanted, free to make implementation and syntax errors (and have them pointed out by ISE). As Xilinx has pushed designers toward PlanAhead and then Vivado, it seems like the direction of design is going towards a higher-level picture that removes some aspects of design control from the designer. Graphical architecture, C to VHDL HLS, and a completely revamped backend that (to my knowledge, I could be wrong) eliminates the ability to simply script builds and modify text-based configuration files. I notice that ISE has entered the "sustaining" phase of its life. This implies that at some point down the road, obsolescence of ISE will become a genuine concern, along with the ability to build for its supported hardware. Not only is the eventual demise of ISE a concern, but the ability to obtain cheap, simple, bare FPGAs with few bells and whistles like the Spartan-6 that can be written for with something as simple as a text editor also seems to be rearing its head. So I guess my questions are these. How long will ISE be supported? How long will the Spartan-6 be available? Are there any plans to maintain a line of simple, stripped-down FPGAs? Will there ever be (or is there now) an option in Vivado to revert to a low-level HDL/UCF design flow like Project Navigator for bare logic designs? Or will Vivado just continue to move design flow from an HDL architecture to a high level function block generator? Thanks for your time.
2019-07-29 07:54
