for SOC/IP, being responsible for front-end verification methodology, test bench and infrastructure.
2012-08-20 18:35
on design language Verilog/VHDL Good knowledge on SystemVerilog, and verification methodology OVM/UVM Good
2012-04-05 23:26
Verilog Synthesis Methodology
2012-08-15 15:31
AMD超威半导体上海研发中心招聘 ASIC Design Verification Engineer；请有意向者将简历发送到 Maggie1.Zhang@amd.com 以及
2017-03-13 16:47
DFT EngineerResponsibilities:· Planning at IP or fullchip level.· Implementation and verification
2016-07-15 13:58
是 Error in HEX file verification 错误 用IAR直接下载出现下面的错误信息，这是什么问题？
2018-06-01 13:09
design3.Familiar with System-Verilog and UVM verification methodology4.Familiar with script languages
2018-09-19 14:15
lucylinxiyang@hotmail.com。本人将定期更新NV最新招聘信息，欢迎长期关注。（本人就是NV的HR,所有岗位都非猎头哦~）SR. PHYSICAL DESIGN METHODOLOGY
2012-07-06 10:09
Writing Testbenches - Functional Verification of HDL Models
2019-12-20 15:08
本帖最后由 NvidiaHR 于 2012-7-6 14:28 编辑 ASIC/SOC Verification Engineer:RESPONSIBILITIES:- RTL design
2012-07-06 14:27
