芯片的设计制造是一个集高精尖于一体的复杂系统工程，难度之高不言而喻。那么，究竟难在何处?
2018-12-27 11:21
前言：多年前，网上出现一组介绍集成电路(芯片)制造的漫画，而且有英文版。无论从专业角度还是漫画角度看，笔者认为漫画画的很棒！可惜网上漫画清晰度不高。笔者对这些漫画进行了清晰化，并配上了通俗的说明文
2020-09-24 17:08
中兴事件让我们认识了中国的“芯”痛，那么小小芯片为什么这么难制造？今天小编给你介绍一下流程。
2019-01-03 10:15
一个国家在国际市场竞争中能否获得优势，芯片制造技术就是关键的影响因素之一。中美贸易摩擦逐渐升级后，许多国产企业都面临被芯片“卡脖子”的困境，国内各大芯片
2022-06-29 16:51
1965年，中国就意识到发展大型集成电路是非常重要的一件事，但在冷战时期，中国尽管以研究两弹一星的体制搞芯片，但直到80年代初，闭关锁国，高新技术与发达国家处在断绝状态，芯片产业没有大的进展。
2020-09-29 11:44
近年来，我国的社会地位和社会经济都在不断提升，科技实力得到了质的飞跃，中国生产的电子产品品质有了长足的进步，技术实力也得到了国内外的认可。但不可否认的是，国产芯片仍在落后于世界先进水平。芯片为什么这么难
2022-07-01 16:48
1. Introduction This document indicates the hardware/software design notes to migrate from Beckhoff ET1100 ESC solution to AX58100 ESC solution. 2. Functions Overview The AX58100 is a 2/3-port EtherCAT Slave Controller (ESC), licensed from Beckhoff Automation, with two integrated Fast Ethernet PHYs which support 100Mbps full-duplex operation and HP Auto-MDIX. AX58100 supports 9 Kbytes Process Data RAM, 8 Fieldbus Memory Management Units (FMMUs), 8 Sync-Managers and a 64-bit Distributed Clock. Compared to other EtherCAT slave controller solutions, the AX58100 integrates two embedded Fast Ethernet PHYs which can support both copper and fiber industrial Ethernet applications and supports some additional interfaces such as Pulse Width Modulation (PWM), Incremental (ABZ)/Hall Encoder, SPI master, 32 Digital I/O, Emergency Stop Input, etc. for designers to easily implement AX58100 on different EtherCAT industrial fieldbus applications without extra microprocessor. The AX58100 provides SPI slave and Local bus Process Data Interfaces (PDI) to provide an easy way for system designers to implement the standard EtherCAT communication functionalities on those traditional non-EtherCAT MCU and DSP industrial platforms. The AX58100 provides a cost-effective EtherCAT slave controller solution for industrial automation, motion/motor/Digital IO control, Digital to Analog (DAC)/Analog to Digital (ADC) converters control, sensors data acquisition, robotics, etc. industrial Ethernet fieldbus applications. The following is the major features comparison between AX58100 and Beckhoff ET1100 ESC solutions.2-1. Block DiagramThe following are the block diagrams of AX58100 and ET1100.Figure 2-1. AX58100 Block DiagramFigure 2-2. ET1100 Block Diagram2-2. Application DiagramThe following are the typical applications diagrams of AX58100 and ET1100. The AX58100 integrates additional interfaces such as Pulse Width Modulation (PWM), ABZ/Hall Encoder, SPI master, 32 Digital I/O, Emergency Stop Input, etc. for designers to easily implement AX58100 on different EtherCAT industrial fieldbus applications without extra microprocessor.Figure 2-4. ET1100 Application Diagram3. Hardware TransitionThis section indicates the hardware design considerations while migrating from Beckhoff ET1100 ESC solution to AX58100 ESC solution. 3-1. Bootstrap Hardware Configuration Pins The AX58100 supports five multi-function bootstrap pins (pin 19, 20, 58, 40, and 41) for five hardware configurations, i.e. external I2C EEPROM size, ESC supported port number, RSTO polarity and integrated port 0/1 PHY media mode; and supports other three multi-function bootstrap pins (pin 42, 52, 66) for the configuration of port 2 MII signals. User needs to utilize an external resistor to pull up/down these bootstrap pins for correct AX58100 hardware configuration. Beckhoff supports different hardware configuration pins based on the ET1100 product design specification. Please refer to Beckhoff ET1100 datasheet for details.3-2. Ethernet Ports The AX58100 ESC, which is licensed from Beckhoff Automation, supports two embedded PHYs and an optional MII interface for flexible network topology. The embedded Fast Ethernet PHYs support 100Mbps full-duplex operation and HP Auto-MDIX, and are fully compliant with the 100BASE-TX and 100BASE-FX Ethernet standards such as IEEE 802.3u, and ANSI X3.263- 1995 (FDDI-TP-PMD) for both copper and fiber industrial Ethernet applications. The optional MII interface of AX58100 ESC is optimized for low processing/forwarding delays by omitting a transmit FIFO. To allow this, the ESC has additional requirements to Ethernet PHY, which is easily accomplished by several PHY vendors. Please refer to Beckhoff’s PHY Selection Guide to select a proper Ethernet PHY. AX58100 Port 0 and Port 1 integrate embedded Ethernet PHYs, and Port 2 is an optional MII interface which are multi-function pins shared with others interfaces (i.e. PWM, Hall, Local Bus, Digital I/O). Packets are forwarded in the following order: Port 0 -> EtherCAT Processing Unit -> Port 1 -> Port 2 AX58100 supports six Bootstrap pins (pin 20, 40-42, 52 and 66) for Ethernet ports hardware configurations. Please refer to Tabel 3-1 for details.The following is the principle connection between AX58100 Port 2 MII interface and Ethernet PHY. The clock source of the Ethernet PHYs and ESC must be the same quartz. The TX_CLK is not connected because the ESCs do not incorporate a TX FIFO. The TX signals can be delayed inside the ESC by setting AX58100 TX_SH[1:0] bootstrap pins for TX_CLK phase shift compensation. The LINK is connected to the PHY LED output indicating a 100 Mbps (Full Duplex) link.
2020-06-17 09:53
因为在科技圈发生的各种问题，比如华为等企业被美国供断芯片，国内一度为芯片供应问题而一筹莫展，很多人也因此知道了芯片的重要性的世界芯片的格局。在
2021-08-27 17:22
我们现在都知道芯片制造的完整过程包括：芯片设计、晶圆制造、封装测试等几个主要环节，每个环节都是尖精技术和先进科技的体现。
2022-07-05 17:55
