电子发烧友

单相电机的启动电容怎么匹配，电容大小不合适会有什么现象？

2023-12-27 07:30

嗨，在周末我一直在玩我的图形设置以提高游戏性能，但是，今天早上连接到我的显示器时，我的显示器的分辨率和缩放都是不合适的。我已经尝试检查所有设置和驱动程序，并测试其他屏幕，但我无法让辅助监视器上

2018-10-15 11:37

就是说我想在打样之前试试封装合不合适，因为排线实在太小，卡尺量不到，直接打样又浪费钱。求大神指导、、、试过用打印机打印出来、、但是不会1：1的比例打出来、、、

2015-12-01 10:51

嗨，我的项目合成确定，但在奇怪的错误实现中断：地点：1012- 已发现时钟IOB / DCM组件对未放置在最佳时钟IOB / DCM站点对。时钟组件放置在现场。如果将时钟IO / DCM站点放置/锁定在同一象限中，则可以将其配对。 IO组件位于站点。这将不允许使用IO和时钟缓冲区之间的快速路径。如果此子设计可接受此子优化条件，则可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为警告并允许您的设计继续。但是，强烈建议不要使用此覆盖，因为它可能导致非常差的时序结果。建议在设计中纠正此错误情况。下面列出了此时钟放置规则中使用的所有COMP.PIN的列表。这些示例可以直接在.ucf文件中使用，以覆盖此时钟规则。地点：1012- 已发现时钟IOB / DCM组件对未放置在最佳时钟IOB / DCM站点对。时钟组件放置在现场。如果将时钟IO / DCM站点放置/锁定在同一象限中，则可以将其配对。 IO组件位于站点。这将不允许使用IO和时钟缓冲区之间的快速路径。如果此子设计可接受此子优化条件，则可以使用.ucf文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为警告并允许您的设计继续。但是，强烈建议不要使用此覆盖，因为它可能导致非常差的时序结果。建议在设计中纠正此错误情况。下面列出了此时钟放置规则中使用的所有COMP.PIN的列表。这些示例可以直接在.ucf文件中使用，以覆盖此时钟规则。我需要两个独立的时钟，我在项目中有两个DCM。似乎实施工具没有最佳地定位DCM。它建议AFAIK手动限制DCM，我不知道如何做到这一点。有人有什么想法吗？我使用了推荐的解决方法 - 核心工作，但它不稳定。同样有趣的是，这个错误并不总是发生。如果我改变一些信号连接，它可能神奇地消失，然后随机重新出现。谢谢，Blaz以上来自于谷歌翻译以下为原文Hi, my projects synthesizes ok, but breaks on implementation on strange error: Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCMsite pair.The clock componentis placed at site .The clock IO/DCM sitecan be paired if they are placed/locked in the same quadrant.The IO componentis placed at site . This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition isacceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this messageto a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it maylead to very poor timing results. It is recommended that this error condition be corrected in the design. A list ofall the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucffile to override this clock rule.< NET "RTDL_CLK_i" CLOCK_DEDICATED_ROUTE = FALSE; >< PIN "RTDL_DecoderCLK/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; >Place:1012 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCMsite pair.The clock componentis placed at site .The clock IO/DCM site canbe paired if they are placed/locked in the same quadrant.The IO componentis placed at site .Thiswill not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition isacceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this messageto a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it maylead to very poor timing results. It is recommended that this error condition be corrected in the design. A list ofall the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucffile to override this clock rule.< NET "EL_CLK_i" CLOCK_DEDICATED_ROUTE = FALSE; >< PIN "EL_DecoderCLK/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; > I need two separate clocks and I have two DCMs in the project. It seems that implementation tools doesn't position DCM optimally. AFAIK it recommends to manualy constraint DCMs, which i don't know how to do it. Anybody has any idea?I used recommended workaround - core works, but it isn't stable. Also interesting is the fact that this error doesn't occur always. If I change some signal connections it could magically disappear, and later on randomly reappear. Thanks,Blaz

2019-05-10 09:29

贴片电阻电容那些小东西，对于新手来说，整理起来比较困难。难道没有什么好方法吗？

2011-06-17 11:44

因为用的激励换能器频率为45MHz，想请问一下，如果用AFE5818来做模数转换(采样频率65M)不合适的话，有没有其他的更高频率的模拟前端？比如说500M或者1000M的？

2024-11-21 06:21

兄弟小白，最近玩穿越机，安装了摄像头和卡录模块，但是TF卡槽位置不合适就想着把卡槽位置延长出来，哪知道延长了七八公分就不能识别TF卡了。已经反复试了几遍（换延长线换卡），最后感觉应该是距离长了就不认卡，哪位大神能支个招看看怎么克服这个问题不胜感激

2024-04-09 13:21